Inventor
James L. Gorecki
Inventor
Hillsboro, OR, US
Overview
Patents· 52 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H04Lprimary
H04LTransmission of digital information, e.g. telegraphic communication17%
H03FAmplifiers13%
H03KPulse technique11%
H03MCoding10%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses9%
H04BTransmission9%
H03GControl of amplification9%
G05FSystems for regulating electric or magnetic variables8%
G11CStatic stores4%
H03HImpedance networks, e.g. resonant circuits4%
PatentTitleYear
10,411,666Open-loop linear VGA201910,110,204Low power buffer with gain boost201810,103,717Low power buffer with dynamic gain control201810,014,836Open-loop linear VGA20189,921,593'Wideband low dropout voltage regulator with power supply rejection boost'20189,866,231'Interleaved successive approximation register analog to digital converter'20189,837,998Low power buffer with dynamic gain control20179,806,722'High frequency delay lock loop systems'20179,716,480'Trans-impedance amplifier with replica gain control'20179,673,972'Phase interpolator'20179,647,643'Low power buffer with gain boost'20179,602,116'Interleaved successive approximation register analog to digital converter'20179,571,077'Dynamic update technique for phase interpolator device and method therefor'20179,552,006'Wideband low dropout voltage regulator with power supply rejection boost'20179,553,569'Low power buffer with dynamic gain control'20179,485,086'Phase interpolator'20169,473,090'Trans-impedance amplifier with replica gain control'20169,438,255'High frequency delay lock loop systems'20169,432,000'Low power buffer with gain boost'20169,160,345'Phase interpolator'20158,031,783'Phase noise shaping using sigma delta modulation in a timing recovery unit'20117,903,729'System and method of equalization of high speed signals'20117,720,160'Phase noise shaping using sigma delta modulation in a timing recovery unit'20107,545,860'System and method of equalization of high speed signals'20097,386,053'System and method of equalization of high speed signals'20087,345,992'System and method for embedding a sub-channel in a block coded data stream'20087,346,119'System and method for high speed digital signaling'20087,345,988'System and method for providing crosstalk management for high-speed signaling links'20087,330,506'System and method for providing variable delay FIR equalizer for serial baseband communications'20087,277,480'System and method of equalization of high speed signals'20077,260,155'Method and apparatus for encoding and decoding digital communications data'20077,248,640'System and method for providing slicer level adaption'20077,233,617'System and method of equalization of high speed signals'20077,230,979'System and method for high speed digital signaling'20077,158,575'System and method for embedding a sub-channel in a block coded data stream'20076,714,066'Integrated programmable continuous time filter with programmable capacitor arrays'20046,701,340'Double differential comparator and programmable analog block architecture using same'20046,556,154'Offset voltage calibration DAC with reduced sensitivity to mismatch errors'20036,424,209'Integrated programmable continuous time filter with programmable capacitor arrays'20025,670,907'VBB reference for pumped substrates'19975,666,087'Active resistor for stability compensation'19975,617,064'Active resistor for stability compensation'19975,574,678'Continuous time programmable analog block architecture'19965,510,738'CMOS programmable resistor-based transconductor'19965,493,205'Low distortion differential transconductor output current mirror'19965,159,205'Timing generator circuit including adjustable tapped delay line within phase lock loop to control timing of signals in the tapped delay line'19925,084,634'Dynamic input sampling switch for CDACS'19925,049,882'High speed analog-to-digital converter'19914,556,866'Power line carrier FSK data system'19854,543,498'Process insensitive CMOS window detector'19854,492,972'JFET Monolithic integrated circuit with input bias current temperature compensation'19854,339,707'Band gap voltage regulator'1982Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1982–1985Patents assigned to HONEYWELL INC (4)· patent assignee history
1982–1985Based in Plymouth, MN, US· patent location history
1985Based in Chandler, AZ, US· patent location history
1991–1992Patents assigned to BURR BROWN CORP (3)· patent assignee history
1991–1992Based in Vail, AZ, US· patent location history
1996–2004Patents assigned to LATTICE SEMICONDUCTOR CORP (9)· patent assignee history
1996–2018Based in Hillsboro, OR, US· patent location history
2007–2011Patents assigned to SYNOPSYS INC (13)· patent assignee history
2015–2019Patents assigned to INPHI CORP (19)· patent assignee history
2016–2019Based in Santa Clara, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INPHI CORP | 19 | 2015–2019 |
| SYNOPSYS INC | 13 | 2007–2011 |
| LATTICE SEMICONDUCTOR CORP | 9 | 1996–2004 |
| HONEYWELL INC | 4 | 1982–1985 |
| BURR BROWN CORP | 3 | 1991–1992 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hillsboro, OR, US | 35 | 1996–2018 |
| Santa Clara, California, US | 10 | 2016–2019 |
| Vail, AZ, US | 3 | 1991–1992 |
| Chandler, AZ, US | 2 | 1985 |
| Plymouth, Minnesota, US | 2 | 1982–1985 |