LexDanaLexDanabeta
Inventor

Ming-Feng Shieh

Inventor
Yongkang City, TW

Overview

105→
Patents
2009–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 105 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1025%
H01LSemiconductor devices24%
H10DInorganic electric semiconductor devices21%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1018%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices10%
G06FElectric digital data processing2%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes0%
PatentTitleYear
11,081,394Method of making a FinFET device202111,037,882Overlay mark202110,770,303Mechanisms for forming patterns using multiple lithography processes202010,755,936Loading effect reduction through multiple coat-etch processes202010,672,656Method of semiconductor integrated circuit fabrication202010,665,467Spacer etching process for integrated circuit design202010,573,751Structure and method for providing line end extensions for fin-type active regions202010,535,646Systems and methods for a sequential spacer scheme202010,424,543Overlay mark201910,410,913Multi-layer metal contacts201910,276,363Mechanisms for forming patterns using multiple lithography processes201910,276,392Loading effect reduction through multiple coat-etch processes201910,249,570Overlay mark201910,163,885Systems and methods for a sequential spacer scheme201810,153,166Mechanisms for forming patterns using lithography processes201810,115,796Method of pulling-back sidewall metal layer201810,096,519Method of making a FinFET device201810,049,885Method for patterning a plurality of features for fin-like field-effect transistor (FinFET) devices201810,049,919Semiconductor device including a target integrated circuit pattern201810,048,590Method and apparatus of patterning a semiconductor device201810,043,759Overlay mark201810,032,664Methods for patterning a target layer through fosse trenches using reverse sacrificial spacer lithography201810,014,175Lithography using high selectivity spacers for pitch reduction20189,929,153'Method of making a FinFET device'20189,917,192'Structure and method for transistors with line end extension'20189,904,163'Cut-mask patterning process for FIN-like field effect transistor (FINFET) device'20189,773,676'Lithography using high selectivity spacers for pitch reduction'20179,761,436'Mechanisms for forming patterns using multiple lithography processes'20179,735,140'Systems and methods for a sequential spacer scheme'20179,711,604'Loading effect reduction through multiple coat-etch processes'20179,673,328'Structure and method for providing line end extensions for fin-type active regions'20179,634,001'System and methods for converting planar design to FinFET design'20179,627,262'Method of patterning features of a semiconductor device'20179,595,440'Method of using a vaporizing spray system to perform a trimming process'20179,581,900'Self aligned patterning with multiple resist layers'20179,576,814'Method of spacer patterning to form a target integrated circuit pattern'20179,564,327'Method for forming line end space structure using trimmed photo resist'20179,524,939'Multiple edge enabled patterning'20169,502,261'Spacer etching process for integrated circuit design'20169,466,486'Method for integrated circuit patterning'20169,443,768'Method of making a FinFET device'20169,437,497'Method of making a FinFET device'20169,437,415'Layer alignment in FinFET fabrication'20169,368,594'Method of forming a fin-like BJT'20169,362,169'Self-aligned semiconductor fabrication with fosse features'20169,362,132'Systems and methods for a sequential spacer scheme'20169,356,021'Self-alignment for two or more layers and methods of forming same'20169,337,083'Multi-layer metal contacts'20169,324,866'Structure and method for transistor with line end extension'20169,305,841'Method of patterning a feature of a semiconductor device'20169,287,125'Multiple edge enabled patterning'20169,281,193'Patterning method for semiconductor device fabrication'20169,252,021'Method for patterning a plurality of features for Fin-like field-effect transistor (FinFET) devices'20169,245,763'Mechanisms for forming patterns using multiple lithography processes'20169,236,267'Cut-mask patterning process for fin-like field effect transistor (FinFET) device'20169,214,356'Mechanisms for forming patterns'20159,190,261'Layer alignment in FinFET fabrication'20159,177,797'Lithography using high selectivity spacers for pitch reduction'20159,153,483'Method of semiconductor integrated circuit fabrication'20159,152,046'Photo-resist with floating acid'20159,153,478'Spacer etching process for integrated circuit design'20159,136,106'Method for integrated circuit patterning'20159,129,839'Method of fabricating a FinFET device'20159,076,736'Patterning method for semiconductor device fabrication'20159,070,630'Mechanisms for forming patterns'20159,069,249'Self aligned patterning with multiple resist layers'20159,054,159'Method of patterning a feature of a semiconductor device'20159,046,785'Method and apparatus of patterning a semiconductor device'20159,040,433'Photo resist trimmed line end space'20159,034,723'Method of making a FinFET device'20159,035,426'Fin-like BJT'20159,026,959'Method and device for increasing fin device density for unaligned fins'20159,023,695'Method of patterning features of a semiconductor device'20158,987,008'Integrated circuit layout and method with double patterning'20158,975,129'Method of making a FinFET device'20158,962,464'Self-alignment for using two or more layers and methods of forming same'20158,936,903'Photo-resist with floating acid'20158,932,957'Method of fabricating a FinFET device'20158,908,181'Overlay mark and method of measuring the same'20148,881,066'Mandrel modification for achieving single fin fin-like field effect transistor (FinFET) device'20148,871,597'High gate density devices and methods'20148,846,490'Method of fabricating a FinFET device'20148,847,295'Structure and method for fabricating fin devices'20148,835,323'Method for integrated circuit patterning'20148,828,885'Photo resist trimmed line end space'20148,816,444'System and methods for converting planar design to FinFET design'20148,802,569'Method of fabricating a semiconductor device'20148,806,397'Method and device for increasing fin device density for unaligned fins'20148,796,156'Cross OD FinFET patterning'20148,795,540'Selective bias compensation for patterning steps in CMOS processes'20148,799,833'System and methods for converting planar design to FinFET design'20148,769,446'Method and device for increasing fin device density for unaligned fins'20148,741,776'Patterning process for fin-like field effect transistor (finFET) device'20148,735,991'High gate density devices and methods'20148,730,473'Multiple edge enabled patterning'20148,525,267'Device and method for forming Fins in integrated circuitry'20138,513,078'Structure and method for fabricating fin devices'20138,486,769'Method for forming metrology structures from fins in integrated circuitry'20138,241,823'Method of fabrication of a semiconductor device having reduced pitch'20128,211,807'Double patterning technology using single-patterning-spacer-technique'20128,110,466'Cross OD FinFET patterning'20128,039,179'Integrated circuit layout design'20117,989,355'Method of pitch halving'20117,862,962'Integrated circuit layout design'20117,476,472'Method for designing photomask'2009

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2009–2020Based in Tainan, TW· patent location history
2011–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (61)· patent assignee history
2011–2021Based in Yongkang City, TW· patent location history
2012–2016Patents assigned to SHIEH MING-FENG (22)· patent assignee history
2013–2015Patents assigned to CHANG CHIH-SHENG (7)· patent assignee history
2013–2016Patents assigned to LIN YI-TANG (7)· patent assignee history
2015–2020Based in Hsinchu, TW· patent location history
2016–2021Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (43)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TAIWAN SEMICONDUCTOR MFG612011–2016
TAIWAN SEMICONDUCTOR MFG CO LTD432016–2021
SHIEH MING-FENGself222012–2016
CHANG CHIH-SHENG72013–2015
LIN YI-TANG72013–2016
Locations
LocationPatentsSpan
Yongkang City, TW712011–2021
Tainan, TW292009–2020
Hsinchu, TW42015–2020