Inventor
Ricardo P. Mikalo
Inventor
Heideblick, DE
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices27%
H01LSemiconductor devices18%
H10BElectronic memory devices12%
G11CStatic stores10%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
G01RMeasuring electric variables6%
B01DSeparation4%
C02FTreatment of water, waste water, sewage, or sludge4%
PatentTitleYear
10,256,134Heat dissipative element for polysilicon resistor bank201910,147,659Method and structure for process limiting yield testing201810,048,311Detection of gate-to-source/drain shorts20189,696,376'Leakage testing of integrated circuits using a logarithmic transducer and a voltmeter'20179,508,618'Staggered electrical frame structures for frame area reduction'20169,368,506'Integrated circuits and methods for operating integrated circuits with non-volatile memory'20169,324,654'Integrated circuits with electronic fuse structures'20169,257,353'Integrated circuits with test structures including bi-directional protection diodes'20169,093,554'Methods of forming semiconductor devices with embedded semiconductor material as source/drain regions using a reduced number of spacers'20159,087,587'Integrated circuits and methods for operating integrated circuits with non-volatile memory'20158,669,170'Methods of reducing gate leakage'20148,642,420'Fabrication of a semiconductor device with extended epitaxial semiconductor regions'20148,536,019'Semiconductor devices having encapsulated isolation regions and related fabrication methods'20138,524,566'Methods for the fabrication of integrated circuits including back-etching of raised conductive structures'20138,476,131'Methods of forming a semiconductor device with recessed source/design regions, and a semiconductor device comprising same'20137,733,698'Memory device, a non-volatile semiconductor memory device and a method of forming a memory device'20107,411,837'Method for operating an electrical writable and erasable memory cell and a memory device for electrical memories'20087,144,776'Charge-trapping memory device'20067,145,807'Method for operating an electrical writable and erasable memory cell and a memory device for electrical memories'20067,015,095'Method for fabricating a semiconductor memory having charge trapping memory cells and semiconductor substrate'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2008Patents assigned to INFINEON TECHNOLOGIES AG (4)· patent assignee history
2006–2008Based in Waltersdorf, DE· patent location history
2010–2019Based in Heideblick, DE· patent location history
2013–2019Patents assigned to GLOBALFOUNDRIES INC (15)· patent assignee history
2013–2015Patents assigned to MIKALO RICARDO P (6)· patent assignee history
2013–2015Patents assigned to FLACHOWSKY STEFAN (5)· patent assignee history
2013–2015Patents assigned to HOENTSCHEL JAN (2)· patent assignee history
2013Based in Heidelblick, DE· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| GLOBALFOUNDRIES INC | 15 | 2013–2019 |
| MIKALO RICARDO Pself | 6 | 2013–2015 |
| FLACHOWSKY STEFAN | 5 | 2013–2015 |
| INFINEON TECHNOLOGIES AG | 4 | 2006–2008 |
| HOENTSCHEL JAN | 2 | 2013–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Heideblick, DE | 15 | 2010–2019 |
| Waltersdorf, DE | 4 | 2006–2008 |
| Heidelblick, DE | 1 | 2013 |