Inventor
OMKAR KARHADE
Inventor
US
Overview
Patents· 38 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1032%
H01LSemiconductor devices30%
G02BOptical elements, systems or apparatus14%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%
G02FOptical devices or arrangements for the control of light by modification of the optical properties of the media of the elements involved therein3%
H10DInorganic electric semiconductor devices3%
H01QAntennas, i.e. radio aerials2%
H05KPrinted circuits2%
F28DHeat-exchange apparatus, not provided for in another subclass, in which the heat-exchange media do not come into direct contact1%
H01FMagnets1%
PatentTitleYear
12,599,050Multi-level die coupled with a substrate202612,599,007Composite IC die package including an electro-thermo-mechanical die (ETMD) with through substrate vias202612,564,090Edge-aligned template structure for integrated packages including an integrated circuit device within an opening of the template structure202612,541,055Electronic device including a lens assembly202612,525,545HBI die fiducial architecture with cantilever fiducials for smaller die size and better yields202612,517,314High bandwidth optical interconnection architectures202612,506,085HBI die architecture with fiducial in street for no metal depopulation in active die202512,500,132Formation of a reconstituted circuit device using flow of a material by capillary action202512,481,108Faraday rotator interconnect as a through-via configuration in a patch architecture202512,476,174Ultra-thin, hyper-density semiconductor packages202512,469,801Moisture seal coating of hybrid bonded stacked die package assembly202512,443,058On-cavity photonic integrated circuit (OCPIC) to achieve the most undercut real estate for effective thermal tuning202512,442,982Temperature sensor to achieve thermal stabilization of micro-ring resonator (MRR) in an open cavity photonic integrated circuit (OCPIC)202512,436,413Undercut design with a bonded base cover for friendly assembly and effective thermal tuning of micro-ring resonator (MRR) in open cavity photonic integrated chips (OCPIC)202512,406,914Ultra-thin, hyper-density semiconductor packages202512,406,893Edge-aligned template structure for integrated circuit packages202512,386,127Micro-lens array optically coupled with a photonics die202512,366,713Heat dissipation structures for optical communication devices202512,334,472Multiple wafer stack architecture to enable singulation202512,327,814Electronic substrate core having an embedded laser stop to control depth of an ultra-deep cavity202512,176,268Open cavity bridge co-planar placement architectures and processes202412,148,744Optical multichip package with multiple system-on-chip dies202412,068,222Dummy die structures of a packaged integrated circuit device202412,061,371Patch on interposer architecture for low cost optical co-packaging202412,044,888Silicon groove architectures and manufacturing processes for passive alignment in a photonics die202412,027,448Open cavity bridge power delivery architectures and processes202412,003,023In-package 3D antenna202411,804,456Wirebond and leadframe magnetic inductors202311,735,495Active package cooling structures using molded substrate packaging technology202311,676,900Electronic assembly that includes a bridge202311,616,2835G mmWave antenna architecture with thermal management202311,611,164Wideband multi-pin edge connector for radio frequency front end module202311,581,240Liquid thermal interface material in electronic packaging202311,574,851Coupled cooling fins in ultra-small systems202311,552,035Electronic package with stud bump electrical connections202311,545,407Thermal management solutions for integrated circuit packages202311,430,724Ultra-thin, hyper-density semiconductor packages202211,222,877Thermally coupled package-on-package semiconductor packages2022Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2022–2026Patents assigned to INTEL CORP (38)· patent assignee history
2022–2026Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 38 | 2022–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 38 | 2022–2026 |