Inventor

Paul R. Culley

Inventor

Cypress, TX, US

Overview

1986–2012

Patent span

Physics

Primary field (CPC G)

Patents· 65 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing87%

H04LTransmission of digital information, e.g. telegraphic communication6%

H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses3%

B41JTypewriters1%

G09GArrangements or circuits for control of indicating devices using static means to present variable information1%

G11CStatic stores1%

PatentTitleYear

8,205,016'Controller receiving a configuration command while receiving an auxiliary supply voltage'2012 8,117,012'Method for determining cooling requirements of a computer system enclosure'2012 7,930,440'Determining electrical compatibility and/or configuration of devices in a pre-boot environment'2011 7,783,876'Comparing characteristics prior to booting devices'2010 7,757,232'Method and apparatus for implementing work request lists'2010 7,617,376'Method and apparatus for accessing a memory'2009 7,565,504'Memory window access mechanism'2009 7,433,763'Power management logic that reconfigures a load when a power supply fails'2008 7,171,484'Reliable datagram transport service'2007 7,103,744'Binding a memory window to a queue pair'2006 7,089,378'Shared receive queues'2006 6,463,529'Processor based system with system wide reset and partial system reset capabilities'2002 6,182,236'Circuit and method employing feedback for driving a clocking signal to compensate for load-induced skew'2001 6,101,322'Removal and insertion of expansion cards in a computer system'2000 6,070,253'Computer diagnostic board that provides system monitoring and permits remote terminal access'2000 6,035,362'Storing data associated with one request while continuing to store data associated with a previous request from the same device'2000 6,032,271'Method and apparatus for identifying faulty devices in a computer system'2000 6,024,486'Data error detection and correction'2000 6,018,620'Double buffering operations between the memory bus and the expansion bus of a computer system'2000 6,000,040'Method and apparatus for diagnosing fault states in a computer system'1999 5,943,482'Expansion card insertion and removal'1999 5,872,939'Bus arbitration'1999 5,872,941'Providing data from a bridge to a requesting device while the bridge is receiving the data'1999 5,870,568'Double buffering operations between the memory bus and the expansion bus of a computer system'1999 5,870,602'Multi-processor system with system wide reset and partial system reset capabilities'1999 5,822,571'Synchronizing data between devices'1998 5,819,053'Computer system bus performance monitoring'1998 5,737,604'Method and apparatus for independently resetting processors and cache controllers in multiple processor systems'1998 5,611,078'Method and apparatus for independently resetting processors and cache controllers in multiple processor systems'1997 5,553,310'Split transactions and pipelined arbitration of microprocessors in multiprocessing computer systems'1996 5,553,248'System for awarding the highest priority to a microprocessor releasing a system bus after aborting a locked cycle upon detecting a locked retry signal'1996 5,519,839'Double buffering operations between the memory bus and the expansion bus of a computer system'1996 5,517,624'Multiplexed communication protocol between central and distributed peripherals in multiprocessor computer systems'1996 5,465,360'Method and apparatus for independently resetting processors and cache controllers in multiple processor systems'1995 5,463,761'Extended duration high resolution timer contained in two integrated circuits and having alternating data sequences provided from different integrated circuits'1995 5,442,753'Circuitry for providing replica data transfer signal during DMA verify operations'1995 5,437,042'Arrangement of DMA, interrupt and timer functions to implement symmetrical processing in a multiprocessor computer system'1995 5,406,590'Method of and apparatus for correcting edge placement errors in multiplying phase locked loop circuits'1995 5,392,436'Two level system bus arbitration having lower priority multiprocessor arbitration and higher priority in a single processor and a plurality of bus masters arbitration'1995 5,367,689'Apparatus for strictly ordered input/output operations for interrupt system integrity'1994 5,341,494'Memory accessing system with an interface and memory selection unit utilizing write protect and strobe signals'1994 5,307,476'Floppy disk controller with DMA verify operations'1994 5,303,364'Paged memory controller'1994 5,247,685'Interrupt handling in an asymmetric multiprocessor computer system'1993 5,214,767'Full address and odd boundary direct memory access controller which determines address size by counting the input address bytes'1993 5,210,847'Noncacheable address random access memory'1993 5,168,568'Delaying arbitration of bus access in digital computers'1992 5,165,037'System for controlling the transferring of different widths of data using two different sets of address control signals'1992 5,163,143'Enhanced locked bus cycle control in a cache memory computer system'1992 5,159,679'Computer system with high speed data transfer capabilities'1992 5,157,774'System for fast selection of non-cacheable address ranges using programmed array logic'1992 5,125,088'Computer system speed control at continuous processor speed'1992 5,109,521'System for relocating dynamic memory address space having received microprocessor program steps from non-volatile memory to address space of non-volatile memory'1992 5,109,332'System for controlling the transferring of different widths of data using two different sets of address control and state information signals'1992 5,101,497'Programmable interrupt controller'1992 5,095,428'Cache flush request circuit flushes the cache if input/output space write operation and circuit board response are occurring concurrently'1992 5,091,850'System for fast selection of non-cacheable address ranges using programmed array logic'1992 5,058,005'Computer system with high speed data transfer capabilities'1991 5,027,313'Apparatus for determining maximum usable memory size'1991 4,999,805'Extended input/output circuit board addressing system'1991 4,835,681'Personal computer having normal and high speed execution modes'1989 4,787,032'Priority arbitration circuit for processor access'1988 4,727,491'Personal computer having normal and high speed execution modes'1988 4,646,077'Video display controller system with attribute latch'1987 4,594,501'Pulse width modulation of printhead voltage'1986

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1986–1987Patents assigned to TEXAS INSTRUMENTS INC (2)· patent assignee history

1986–2012Based in Houston, TX, US· patent location history

1988–2001Patents assigned to COMPAQ COMPUTER CORP (49)· patent assignee history

1989–2002Based in Cypress, TX, US· patent location history

2001–2012Based in Tomball, TX, US· patent location history

2006–2012Patents assigned to HEWLETT PACKARD DEVELOPMENT CO (10)· patent assignee history

2007–2012Patents assigned to CULLEY PAUL R (3)· patent assignee history

2007Patents assigned to BENNER ALAN F (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
COMPAQ COMPUTER CORP	49	1988–2001
HEWLETT PACKARD DEVELOPMENT CO	10	2006–2012
CULLEY PAUL Rself	3	2007–2012
TEXAS INSTRUMENTS INC	2	1986–1987
BENNER ALAN F	1	2007

Locations

Location	Patents	Span
Cypress, Texas, US	47	1989–2002
Tomball, Texas, US	10	2001–2012
Houston, Texas, US	8	1986–2012