Inventor
Tiao-Yuan Huang
Inventor
Cupertino, CA, US
Overview
Patents· 36 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices52%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests13%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
H01LSemiconductor devices7%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
B82YSpecific uses or applications of nanostructures2%
E05DHinges or suspension devices for doors, windows or wings2%
E05YIndexing scheme associated with subclasses e05d and e05f, relating to construction elements, electric control, power supply, power signal or transmission, user interfaces, mounting or coupling, details, accessories, auxiliary operations not otherwise provided for, application thereof2%
F16CShafts2%
G06FElectric digital data processing2%
PatentTitleYear
11,132,030Electronic device20219,653,552'Body-tied, strained-channel multi-gate device and methods'20179,406,800'Body-tied, strained-channel multi-gate device and methods of manufacturing same'20169,214,554'Body-tied, strained-channel multi-gate device and methods of manufacturing same'20158,946,811'Body-tied, strained-channel multi-gate device and methods of manufacturing same'20156,894,352'Single-electron transistor and fabrication method thereof'20056,667,508'Nonvolatile memory having a split gate'20036,555,424'Thin film transistor with sub-gates and schottky source/drain and a manufacturing method of the same'20036,495,432'Method of improving a dual gate CMOS transistor to resist the boron-penetrating effect'20026,432,786'Method of forming a gate oxide layer with an improved ability to resist the process damage'20026,232,206'Method for forming electrostatic discharge (ESD) protection transistors'20016,087,189'Test structure for monitoring overetching of silicide during contact opening'20005,998,246'Self-aligned manufacturing method of a thin film transistor for forming a single-crystal bottom-gate and an offset drain'19995,893,741'Method for simultaneously forming local interconnect with silicided elevated source/drain MOSFET\'s'19995,827,768'Method for manufacturing an MOS transistor having a self-aligned and planarized raised source/drain structure'19985,814,544'Forming a MOS transistor with a recessed channel'19985,783,479'Structure and method for manufacturing improved FETs having T-shaped gates'19985,716,860'CMOS input buffer with NMOS gate coupled to Vss through undoped gate poly resistor'19985,618,740'Method of making CMOS output buffer with enhanced ESD resistance'19975,581,105'CMOS input buffer with NMOS gate coupled to V.sub.SS through undoped gate poly resistor'19965,529,941'Method for making an integrated circuit structure'19965,517,049'CMOS output buffer with enhanced ESD resistance'19965,510,728'Multi-finger input buffer with transistor gates capacitively coupled to ground'19965,418,391'Semiconductor-on-insulator integrated circuit with selectively thinned channel region'19955,413,969'Differential treatment to selectively avoid silicide formation on ESD I/O transistors in a salicide process'19955,394,358'SRAM memory cell with tri-level local interconnect'19955,386,134'Asymmetric electro-static discharge transistors for increased electro-static discharge hardness'19955,342,798'Method for selective salicidation of source/drain regions of a transistor'19945,038,184'Thin film varactors'19914,988,638'Method of fabrication a thin film SOI CMOS device'19914,963,504'Method for fabricating double implanted LDD transistor self-aligned with gate'19904,951,113'Simultaneously deposited thin film CMOS TFTs and their method of fabrication'19904,945,067'Intra-gate offset high voltage thin film transistor with misalignment immunity and method of its fabrication'19904,907,048'Double implanted LDD transistor self-aligned with gate'19904,907,041'Intra-gate offset high voltage thin film transistor with misalignment immunity'19904,904,611'Formation of large grain polycrystalline films'1990Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1990–1991Patents assigned to XEROX CORP (8)· patent assignee history
1990–2017Based in Cupertino, CA, US· patent location history
1994–1998Patents assigned to VLSI TECHNOLOGY INC (12)· patent assignee history
1998–2002Patents assigned to NAT SCIENCE COUNCIL (7)· patent assignee history
1998–2005Based in Hsinchu, TW· patent location history
2015Patents assigned to TAIWAN SEMICONDUCTOR MFG (2)· patent assignee history
2016–2017Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (2)· patent assignee history
2021Based in Taipei, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| VLSI TECHNOLOGY INC | 12 | 1994–1998 |
| XEROX CORP | 8 | 1990–1991 |
| NAT SCIENCE COUNCIL | 7 | 1998–2002 |
| TAIWAN SEMICONDUCTOR MFG | 2 | 2015 |
| TAIWAN SEMICONDUCTOR MFG CO LTD | 2 | 2016–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Cupertino, California, US | 24 | 1990–2017 |
| Hsinchu, TW | 11 | 1998–2005 |
| Taipei, TW | 1 | 2021 |