Inventor
Elan Banin
Inventor
Raanana, IL
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Lprimary
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses23%
H04LTransmission of digital information, e.g. telegraphic communication21%
H04BTransmission16%
G04FTime-interval measuring11%
H03MCoding5%
H04WWireless communication networks5%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems4%
G01RMeasuring electric variables2%
G11BInformation storage based on relative movement between record carrier and transducer2%
H01QAntennas, i.e. radio aerials2%
PatentTitleYear
11,121,731Digital radio head control202111,095,427Transceiver with inseparable modulator demodulator circuits202111,088,891Methods and devices generating a calibration signal for an IQ imbalance202110,788,794DTC based carrier shift--online calibration202010,768,580Time-to-digital converter, digital phase-locked loop, method for operating a time-to-digital converter, and method for a digital phase-locked loop202010,707,880Circuit, apparatus, digital phase locked loop, receiver, transceiver, mobile device, method and computer program to reduce noise in a phase signal202010,686,451DPLL with adjustable delay in integer operation mode202010,680,619Digital phase locked loop frequency estimation202010,659,061Divider-less fractional PLL architecture202010,459,407DTC based carrier shift--online calibration201910,263,624Phase synchronization between two phase locked loops201910,181,856Digital phase locked loop frequency estimation201910,027,356Zero-cross-pre-distortion (ZCPD) algorithm for DTC based polar DTx20189,923,563'Deterministic jitter removal using a closed loop digital-analog mechanism'20189,912,357'Digital polar transmitter having a digital front end'20189,698,863'Methods and arrangements for spur estimation of a wireless communication packet'20179,571,107'High-order sigma delta for a divider-less digital phase-locked loop'20179,419,829'Apparatus, system and method of direct current (DC) estimation of a wireless communication packet'20169,374,197'Methods and arrangements for direct current estimation of a wireless communication packet'20169,231,602'A-priori-probability-phase-estimation for digital phase-locked loops'20169,106,502'Apparatus, system and method of in-phase/quadrature (I/Q) imbalance compensation'2015Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2015–2021Patents assigned to INTEL CORP (9)· patent assignee history
2015–2021Based in Raanana, IL· patent location history
2016–2020Patents assigned to INTEL IP CORP (12)· patent assignee history
2020Patents assigned to APPLE INC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL IP CORP | 12 | 2016–2020 |
| INTEL CORP | 9 | 2015–2021 |
| APPLE INC | 1 | 2020 |
Locations
| Location | Patents | Span |
|---|---|---|
| Raanana, IL | 20 | 2015–2021 |