LexDanaLexDanabeta
Inventor

Marco Pasotti

Inventor
San Martino Siccomario, IT

Overview

75→
Patents
1998–2021
Patent span
Physics
Primary field (CPC G)

Patents· 75 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores72%
G06FElectric digital data processing6%
G05FSystems for regulating electric or magnetic variables4%
G01RMeasuring electric variables2%
H01LSemiconductor devices2%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems2%
H03FAmplifiers2%
H03KPulse technique2%
H10BElectronic memory devices2%
H04LTransmission of digital information, e.g. telegraphic communication1%
PatentTitleYear
11,133,064Latch-type sense amplifier for a non-volatile memory with reduced margin between supply voltage and bitline-selection voltage202110,978,146Single-ended phase-change memory device and reading method202110,755,777Transformed non-reprogrammable memory array devices and methods of manufacture202010,319,438Memory with margin current addition and related methods201910,292,069System and method for multi-channel packet transmission201910,176,869Memory device including decoder for a program pulse and related methods201910,139,850Analog boost circuit for fast recovery of mirrored current201810,109,329Identification of a condition of a sector of memory cells in a non-volatile memory201810,068,643Sense amplifier for non-volatile memory devices and related methods201810,049,736Memory device including decoder for a program pulse and related methods20189,991,000Memory with margin current addition and related methods20189,921,598'Analog boost circuit for fast recovery of mirrored current'20189,893,689'System and method for a multistage operational amplifier'20189,691,493'Device for generating a voltage reference comprising a non-volatile memory cell'20179,646,684'PCM memory with margin current addition and related methods'20179,640,230'Identification of an operational condition of a sector of memory cells in a non-volatile memory'20179,634,562'Voltage doubling circuit and charge pump applications for the voltage doubling circuit'20179,627,066'Non volatile memory cell and memory array'20179,613,696'Memory device including decoder for a program pulse and related methods'20179,613,692'Sense amplifier for non-volatile memory devices and related methods'20179,466,347'Row decoder for non-volatile memory devices and related methods'20169,443,566'Identification of a condition of a sector of memory cells in a non-volatile memory'20169,442,149'Measuring leakage currents and measuring circuit for carrying out such measuring'20169,349,490'Error correction in differential memory devices with reading in single-ended mode in addition to reading in differential mode'20169,324,399'System and method for a level shifting decoder'20169,286,160'System and method for phase change memory with erase flag cells'20169,025,355'Non-volatile memory device with clustered memory cells'20158,693,256'FTP memory device with single selection transistor'20148,619,469'FTP memory device with programming and erasing based on Fowler-Nordheim effect'20138,493,787'FTP memory device programmable and erasable at cell level'20138,264,872'Column decoder for non-volatile memory devices, in particular of the phase-change type'20127,885,116'Sense amplifier for low-supply-voltage nonvolatile memory cells'20117,843,255'Charge pump regulator and circuit structure'20107,835,201'Level-shifter circuit and memory device comprising said circuit'20107,508,716'Sense amplifier for low-supply-voltage nonvolatile memory cells'20097,504,862'Level shifter translator'20097,360,068'Reconfigurable signal processing IC with an embedded flash memory device'20087,251,705'Embeddable flash memory system for non-volatile storage of code, data and bit-streams for embedded FPGA configurations'20077,110,289'Method and system for controlling MRAM write current to reduce power consumption'20067,088,614'Programming method for a multilevel memory cell'20066,897,710'Voltage supply distribution architecture for a plurality of memory modules'20056,894,934'Non-volatile memory cell sensing circuit, particularly for low power supply voltages and high capacitive load values'20056,839,818'Electrically modifiable, non-volatile, semiconductor memory which can keep a datum stored until an operation to modify the datum is completed'20056,687,159'Method of programming a plurality of memory cells connected in parallel, and a programming circuit therefor'20046,687,167'EEPROM flash memory erasable line by line'20046,667,903'Programming method for a multilevel memory cell'20036,655,758'Method for storing data in a nonvolatile memory'20036,622,106'Device for testing and calibrating the oscillation frequency of an integrated oscillator'20036,581,134'Logic partitioning of a nonvolatile memory array'20036,535,428'Sensing circuit for memory cells'20036,473,340'Reading method and circuit for a non-volatile memory'20026,469,934'Soft programming method for non-volatile memory cells'20026,466,481'Device and method for programming nonvolatile memory cells with automatic generation of programming voltage'20026,400,607'Reading circuit for a non-volatile memory'20026,392,931'Method for high precision programming nonvolatile memory cells, with optimized programming speed'20026,381,177'Method for controlled soft programming of non-volatile memory cells, in particular of the flash EEPROM and EPROM type'20026,323,799'Device for reading non-volatile memory cells in particular analog flash memory cells'20016,314,043'Erasing and parallel rewriting circuit for memory cell blocks, particularly for analog flash cells, and related operating method'20016,292,398'Method for the in-writing verification of the threshold value in non-volatile memories'20016,282,125'Method for erasing and rewriting non volatile memory cells and particularly flash cells'20016,259,626'Method for storing bytes in multi-level non-volatile memory cells'20016,232,753'Voltage regulator for driving plural loads based on the number of loads being driven'20016,195,289'Device for reading analog nonvolatile memory cells, in particular flash cells'20016,195,283'Method and device for analog programming of non-volatile memory cells'20016,169,691'Method for maintaining the memory content of non-volatile memory cells'20016,163,483'Circuit for parallel programming nonvolatile memory cells, with adjustable programming speed'20006,128,228'Circuit for high-precision analog reading of nonvolatile memory cells, in particular analog or multilevel flash or EEPROM memory cells'20006,091,642'Method for controlled erasing memory devices, in particular analog and multi-level flash-EEPROM devices'20006,081,448'Method and device for analog programming of flash EEPROM memory cells with autoverify'20006,069,822'Method for parallel programming of nonvolatile memory devices, in particular flash memories and EEPROMS'20006,034,888'Reading circuit for nonvolatile analog memories, in particular flash-eeprom memories, with direct and constant current threshold voltage reading'20006,016,272'High-precision analog reading circuit for flash analog memory arrays using negative feedback'20006,011,715'Method for multilevel programming of a nonvolatile memory, and a multilevel nonvolatile memory'20005,973,959'Circuit and method of reading cells of an analog memory array, in particular of the flash type'19995,805,492'Analog memory for storing a QCIF image or the like as electric charge'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2019Based in San Martino Siccomario, IT· patent location history
1999–2021Patents assigned to ST MICROELECTRONICS SRL (71)· patent assignee history
2001–2006Based in S. Martino Sicc., IT· patent location history
2005–2006Based in Pavia, IT· patent location history
2009–2019Patents assigned to PASOTTI MARCO (7)· patent assignee history
2009–2012Patents assigned to DE SANDRE GUIDO (3)· patent assignee history
2010–2021Based in Travaco' Siccomario, IT· patent location history
2013–2014Patents assigned to LENA DAVIDE (3)· patent assignee history
2015–2019Patents assigned to ST MICROELECTRONICS INT NV (9)· patent assignee history
2017–2018Based in Travaco′ Sicomario, IT· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
ST MICROELECTRONICS SRL711999–2021
ST MICROELECTRONICS INT NV92015–2019
PASOTTI MARCOself72009–2019
DE SANDRE GUIDO32009–2012
LENA DAVIDE32013–2014
Locations
LocationPatentsSpan
San Martino Siccomario, IT391998–2019
Travaco' Siccomario, IT242010–2021
S. Martino Sicc., IT72001–2006
Travaco′ Sicomario, IT22017–2018
Pavia, IT22005–2006