Inventor
Christopher P. Ausschnitt
Inventor
Brookfield, CT, US
Overview
Patents· 64 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G03Fprimary
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices55%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
G01BMeasuring length, thickness or similar linear dimensions6%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
H01LSemiconductor devices4%
H10DInorganic electric semiconductor devices4%
G01NInvestigating or analysing materials by determining their chemical or physical properties3%
G05BControl or regulating systems in general3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems2%
PatentTitleYear
10,824,081Metrology method for a semiconductor manufacturing process202010,656,535Metrology method for a semiconductor manufacturing process202010,481,504Method and apparatus for semiconductor manufacturing20199,411,249'Differential dose and focus monitor'20169,360,858'Alignment data based process control system'20169,257,351'Metrology marks for bidirectional grating superposition patterning processes'20169,097,989'Target and method for mask-to-wafer CD, pattern placement and overlay measurement and control'20159,087,740'Fabrication of lithographic image fields using a proximity stitch metrology'20159,059,102'Metrology marks for unidirectional grating superposition patterning processes'20158,874,249'Discrete sampling based nonlinear control system'20148,847,416'Multi-layer chip overlay target and measurement'20148,638,438'Self-calibrated alignment and overlay target and measurement'20148,626,328'Discrete sampling based nonlinear control system'20148,361,683'Multi-layer chip overlay target and measurement'20138,339,605'Multilayer alignment and overlay target and measurement method'20128,107,079'Multi layer alignment and overlay target and measurement method'20128,035,824'Differential critical dimension and overlay metrology apparatus and measurement method'20117,957,826'Methods for normalizing error in photolithographic processes'20117,879,515'Method to control semiconductor device overlay using post etch image metrology'20117,876,439'Multi layer alignment and overlay target and measurement method'20117,700,247'Differential critical dimension and overlay metrology apparatus and measurement method'20107,626,702'Overlay target and measurement method using reference and sub-grids'20097,585,601'Method to optimize grating test pattern for lithography monitoring and control'20097,474,401'Multi-layer alignment and overlay target and measurement method'20097,455,939'Method of improving grating test pattern for lithography monitoring and controlling'20087,439,001'Focus blur measurement and control method'20087,359,054'Overlay target and measurement method using reference and sub-grids'20087,042,551'Method of patterning process metrology based on the intrinsic focus offset'20066,975,398'Method for determining semiconductor overlay on groundrule devices'20056,937,337'Overlay target and measurement method using reference and sub-grids'20056,879,400'Single tone process window metrology target and method for lithographic processing'20056,869,739'Integrated lithographic print and detection model for optical CD'20056,842,237'Phase shifted test pattern for monitoring focus and aberrations in optical projection systems'20056,803,995'Focus control system'20046,766,211'Structure and method for amplifying target overlay errors using the synthesized beat signal between interleaved arrays of differing periodicity'20046,638,671'Combined layer-to-layer and within-layer overlay control system'20036,460,265'Double-sided wafer exposure method and device'20026,429,667'Electrically testable process window monitor for lithographic processing'20026,417,929'Optical measurement of lithographic power bias of minimum features'20026,346,979'Process and apparatus to adjust exposure dose in lithography systems'20026,335,151'Micro-surface fabrication process'20026,317,211'Optical metrology tool and method of using same'20016,183,919'Darkfield imaging for enhancing optical detection of edges and minimum features'20016,137,578'Segmented bar-in-bar target'20006,130,750'Optical metrology tool and method of using same'20006,128,089'Combined segmented and nonsegmented bar-in-bar targets'20006,027,842'Process for controlling etching parameters'20006,020,966'Enhanced optical detection of minimum features using depolarization'20006,004,706'Etching parameter control system process'19995,976,740'Process for controlling exposure dose or focus parameters using tone reversing pattern'19995,965,309'Focus or exposure dose parameter control system using tone reversing patterns'19995,953,128'Optically measurable serpentine edge tone reversed targets'19995,914,784'Measurement method for linewidth metrology'19995,877,861'Method for overlay control system'19995,805,290'Method of optical metrology of unresolved pattern arrays'19985,790,254'Monitoring of minimum features on a substrate'19985,757,507'Method of measuring bias and edge overlay error for sub-0.5 micron ground rules'19985,731,877'Automated system utilizing self-labeled target by pitch encoding'19985,712,707'Edge overlay measurement target for sub-0.5 micron ground rules'19985,629,772'Monitoring of minimum features on a substrate'19974,890,239'Lithographic process analysis and control system'19894,538,105'Overlay test wafer'19854,290,384'Coating apparatus'19814,166,219'Detection of ground state hydrogen and deuterium'1979Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1997–2016Patents assigned to IBM (55)· patent assignee history
1997–2005Based in Brookfield, CT, US· patent location history
2003–2012Based in Lexington, MA, US· patent location history
2009–2015Based in Boston, MA, US· patent location history
2012–2016Patents assigned to AUSSCHNITT CHRISTOPHER P (7)· patent assignee history
2012–2015Patents assigned to MORILLO JAIME D (3)· patent assignee history
2014–2016Based in Naples, FL, US· patent location history
2016Patents assigned to GLOBALFOUNDRIES INC (3)· patent assignee history
2019–2020Patents assigned to IMEC VZW (3)· patent assignee history
2019–2020Based in Heverlee, BE· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 55 | 1997–2016 |
| AUSSCHNITT CHRISTOPHER Pself | 7 | 2012–2016 |
| GLOBALFOUNDRIES INC | 3 | 2016 |
| IMEC VZW | 3 | 2019–2020 |
| MORILLO JAIME D | 3 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Brookfield, CT, US | 27 | 1997–2005 |
| Lexington, Massachusetts, US | 15 | 2003–2012 |
| Naples, Florida, US | 7 | 2014–2016 |
| Boston, Massachusetts, US | 4 | 2009–2015 |
| Heverlee, BE | 3 | 2019–2020 |