Inventor

David Naura

Inventor

Aix en Provence, FR

Overview

40→

Patents

1998–2013

Patent span

Physics

Primary field (CPC G)

Patents· 40 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores59%

H03KPulse technique14%

G06KGraphical data reading8%

G06FElectric digital data processing6%

H04LTransmission of digital information, e.g. telegraphic communication4%

G05FSystems for regulating electric or magnetic variables2%

H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses2%

H10BElectronic memory devices2%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%

PatentTitleYear

8,410,910'Passive contactless integrated circuit comprising a flag for monitoring an erase/programming voltage'2013 8,180,992'Method for configuring a memory space divided into memory banks'2012 8,022,889'Antenna impedance modulation method'2011 7,881,124'Method for block writing in a memory'2011 7,801,940'Method for dividing a number by a fraction having a number in the form of a power of 2 at the numerator'2010 7,679,945'Persistent volatile memory with sense amplifier and discharge switch'2010 7,675,341'Method and device for generating a clock signal'2010 7,614,564'Clock generation method and device for decoding from an asynchronous data signal'2009 7,602,878'Binary frequency divider'2009 7,460,401'Method for checking block erasing of a memory and circuit thereof'2008 7,447,080'Method and device for checking the execution of a write command for writing in a memory'2008 7,436,702'Integrated circuit with a data memory protected against UV erasure'2008 7,237,157'Procedure and device for identifying an operating mode of a controlled device'2007 7,012,837'Method for erasing/programming a non-volatile electrically erasable memory'2006 6,714,450'Word programmable EEPROM memory comprising column selection latches with two functions'2004 6,621,737'Circuit and associated method for the erasure or programming of a memory cell'2003 6,538,931'Methods of operating an integrated circuit with memory having an internal circuit for the generation of a programming high voltage'2003 6,504,791'Method for page mode writing in an electrically erasable/programmable non-volatile memory and corresponding architecture'2003 6,385,096'Memory incorporating column register and method of writing in said memory'2002 6,359,822'Serial access integrated circuit memory'2002 6,324,117'Method of selecting a memory access line and an access line decoder for performing the same'2001 6,307,792'Memory incorporating column register and method of writing in said memory'2001 6,275,413'Architecture of a non-volatile electrically erasable and programmable memory'2001 6,219,277'Device and method for the reading of EEPROM cells'2001 6,212,112'Method to verify the integrity of the decoding circuits of a memory'2001 6,157,227'Device for neutralization in an integrated circuit'2000 6,127,898'Ring oscillator using CMOS technology'2000 6,125,063'Integrated circuit with memory comprising an internal circuit for the generation of a programming high voltage'2000 6,125,022'Device to neutralize an electronic circuit when it is being powered or disconnected'2000 6,118,709'Externally controlled power on reset device for non-volatile memory in integrated circuit form'2000 6,040,994'Method for writing in an electrically modifiable non-volatile memory'2000 6,034,895'Method and circuit for the programming and erasure of a memory'2000 5,999,447'Non-volatile electrically erasable and programmable memory'1999 5,995,416'Method and circuit for the generation of programming and erasure voltage in a non-volatile memory'1999 5,978,268'Circuit for the generation of voltage for the programming or erasure of a memory that uses floating-gate transistors'1999 5,946,241'Non-volatile memory in integrated circuit form with fast reading'1999 5,886,549'Device to neutralize an electronic circuit when it is being powered or disconnected'1999 5,883,833'Method and circuit for the programming and erasure of a memory'1999 5,883,831'Serial access memory with securing of write operations'1999 5,841,270'Voltage and/or current reference generator for an integrated circuit'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2000Patents assigned to SGS THOMSON MICROELECTRONICS (7)· patent assignee history

1998Based in Tivoli, IT· patent location history

1999–2013Patents assigned to ST MICROELECTRONICS SA (31)· patent assignee history

1999–2013Based in Aix en Provence, FR· patent location history

2000Based in Batiment, FR· patent location history

2012–2013Patents assigned to KARI AHMED (2)· patent assignee history

2012–2013Patents assigned to MOREAUX CHRISTOPHE (2)· patent assignee history

2012–2013Patents assigned to NAURA DAVID (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
ST MICROELECTRONICS SA	31	1999–2013
SGS THOMSON MICROELECTRONICS	7	1998–2000
KARI AHMED	2	2012–2013
MOREAUX CHRISTOPHE	2	2012–2013
NAURA DAVIDself	2	2012–2013

Locations

Location	Patents	Span
Aix en Provence, FR	38	1999–2013
Batiment, FR	1	2000
Tivoli, IT	1	1998