Inventor
Sungjun Chun
Inventor
Austin, TX, US
Overview
Patents· 35 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing28%
H05KPrinted circuits27%
Y10TTechnical subjects covered by former us classification19%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
Y02PClimate change mitigation technologies in the production or processing of goods8%
G01RMeasuring electric variables3%
H01RElectrically-conductive connections3%
H01QAntennas, i.e. radio aerials1%
H04BTransmission1%
H04WWireless communication networks1%
PatentTitleYear
11,031,965Small antenna apparatus and method for controlling the same202110,657,308Signal via positioning in a multi-layer circuit board202010,375,820Crosstalk reduction between signal layers in a multilayered package by variable-width mesh plane structures201910,223,490Signal via positioning in a multi-layer circuit board using a genetic via placement solver201910,216,884Signal via positioning in a multi-layer circuit board using a genetic via placement solver201910,135,162Method for fabricating a hybrid land grid array connector201810,128,593Connector having a body with a conductive layer common to top and bottom surfaces of the body as well as to wall surfaces of a plurality of holes in the body20189,980,382Method of making a printed circuit board copper plane repair20189,955,567Crosstalk reduction between signal layers in a multilayered package by variable-width mesh plane structures20189,940,426Signal via positioning in a multi-layer circuit board20189,916,410'Signal via positioning in a multi-layer circuit board'20189,881,115'Signal via positioning in a multi-layer circuit board using a genetic via placement solver'20189,875,331Signal via positioning in a multi-layer circuit board using a genetic via placement solver20189,485,866'Printed circuit board copper plane repair'20169,477,568'Managing interconnect electromigration effects'20169,374,910'Printed circuit board copper plane repair'20169,357,649'276-pin buffered memory card with enhanced memory system interconnect'20168,962,475'Multi-layer circuit substrate fabrication method providing improved transmission line integrity and increased routing density'20158,927,879'Crosstalk reduction between signal layers in a multilayered package by variable-width mesh plane structures'20158,813,000'System for designing substrates having reference plane voids with strip segments'20148,645,889'Noise coupling reduction and impedance discontinuity control in high-speed ceramic modules'20148,638,567'Circuit manufacturing and design techniques for reference plane voids with strip segment'20148,625,300'Circuit manufacturing and design techniques for reference plane voids with strip segment'20148,624,297'Multi-layer circuit substrate fabrication and design methods providing improved transmission line integrity and increased routing density'20148,407,644'Reducing crosstalk in the design of module nets'20138,325,490'Circuit manufacturing and design techniques for reference plane voids with strip segment'20128,288,657'Noise coupling reduction and impedance discontinuity control in high-speed ceramic modules'20128,257,092'Redundant clock channel for high reliability connectors'20127,945,881'Method of reducing crosstalk induced noise in circuitry designs'20117,868,608'Detecting open ground connections in surface mount connectors'20117,821,796'Reference plane voids with strip segment for improving transmission line integrity over vias'20107,646,082'Multi-layer circuit substrate and method having improved transmission line integrity and increased routing density'20107,348,667'System and method for noise reduction in multi-layer ceramic packages'20087,313,747'Measuring microprocessor susceptibility to internal noise generation'20076,789,241'Methodology for determining the placement of decoupling capacitors in a power distribution system'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2020Based in Austin, TX, US· patent location history
2007–2020Patents assigned to IBM (32)· patent assignee history
2012–2016Patents assigned to CHUN SUNGJUN (10)· patent assignee history
2012–2014Patents assigned to HARIDASS ANAND (7)· patent assignee history
2012–2015Patents assigned to WEEKLY ROGER D (5)· patent assignee history
2012–2015Patents assigned to CHOI JINWOO (3)· patent assignee history
2021Based in Suwon-si, KR· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 32 | 2007–2020 |
| CHUN SUNGJUNself | 10 | 2012–2016 |
| HARIDASS ANAND | 7 | 2012–2014 |
| WEEKLY ROGER D | 5 | 2012–2015 |
| CHOI JINWOO | 3 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 34 | 2004–2020 |
| Suwon-si, KR | 1 | 2021 |