Inventor

Darlene G. Hamilton

Inventor

San Jose, CA, US

Overview

1997–2015

Patent span

Physics

Primary field (CPC G)

Patents· 69 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores72%

H10BElectronic memory devices7%

H10DInorganic electric semiconductor devices7%

B82YSpecific uses or applications of nanostructures3%

G01RMeasuring electric variables1%

H01BCables1%

H01LSemiconductor devices1%

H10KOrganic electric solid-state devices1%

H10NElectric solid-state devices not otherwise provided for1%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h101%

PatentTitleYear

8,941,094'Methods for adjusting the conductivity range of a nanotube fabric layer'2015 8,938,655'Extending flash memory data retension via rewrite refresh'2015 8,619,450'Method for adjusting a resistive change element using a reference'2013 8,559,255'Controlling AC disturbance while programming'2013 8,391,070'Moving program verify level for programming of memory'2013 8,264,898'Controlling AC disturbance while programming'2012 8,000,127'Method for resetting a resistive change memory element'2011 7,995,386'Applying negative gate voltage to wordlines adjacent to wordline associated with read or verify to reduce adjacent wordline disturb'2011 7,986,562'Controlling AC disturbance while programming'2011 7,872,916'Deterministic-based programming in memory'2011 7,821,840'Multi-phase programming of multi-level memory'2010 7,692,962'Reduced state quadbit'2010 7,679,967'Controlling AC disturbance while programming'2010 7,672,803'Input of test conditions and output generation for built-in self test'2010 7,656,705'Fast single phase program algorithm for quadbit'2010 7,652,919'Multi-level operation in dual element cells using a supplemental programming level'2010 7,626,869'Multi-phase wordline erasing for flash memory'2009 7,443,732'High performance flash memory device capable of high density data storage'2008 7,440,333'Method of determining voltage compensation for flash memory devices'2008 7,415,646'Pageâ€”EXE erase algorithm for flash memory'2008 7,284,167'Automated tests for built-in self test'2007 7,283,402'Methods and systems for high write performance in multi-bit flash memory devices'2007 7,251,158'Erase algorithm for multi-level bit flash memory'2007 7,206,224'Methods and systems for high write performance in multi-bit flash memory devices'2007 7,130,210'Multi-level ONO flash program algorithm for threshold width control'2006 7,113,431'Quad bit using hot-hole erase for CBD control'2006 7,103,706'System and method for multi-bit flash reads using dual dynamic references'2006 7,068,204'System that facilitates reading multi-level data in non-volatile memory'2006 7,038,948'Read approach for multi-level virtual ground memory'2006 7,038,950'Multi bit program algorithm'2006 7,023,740'Substrate bias for programming non-volatile memory'2006 7,009,887'Method of determining voltage compensation for flash memory devices'2006 7,010,736'Address sequencer within BIST (Built-in-Self-Test) system'2006 6,967,873'Memory device and method using positive gate stress to recover overerased cell'2005 6,956,768'Method of programming dual cell memory device to store multiple data states per cell'2005 6,944,057'Method to obtain temperature independent program threshold voltage distribution using temperature dependent voltage reference'2005 6,901,010'Erase method for a dual bit memory cell'2005 6,897,110'Method of protecting a memory array from charge damage during fabrication'2005 6,822,909'Method of controlling program threshold voltage distribution of a dual cell memory device'2004 6,813,752'Method of determining charge loss activation energy of a memory array'2004 6,799,256'System and method for multi-bit flash reads using dual dynamic references'2004 6,791,880'Non-volatile memory read circuit with end of life simulation'2004 6,788,583'Pre-charge method for reading a non-volatile memory cell'2004 6,778,442'Method of dual cell memory device operation for improved end-of-life read margin'2004 6,775,187'Method of programming a dual cell memory device'2004 6,771,545'Method for reading a non-volatile memory cell adjacent to an inactive region of a non-volatile memory cell array'2004 6,768,673'Method of programming and reading a dual cell memory device'2004 6,743,677'Method for fabricating nitride memory cells using a floating gate fabrication process'2004 6,735,114'Method of improving dynamic reference tracking for flash memory unit'2004 6,707,078'Dummy wordline for erase and bitline leakage'2004 6,631,086'On-chip repair of defective address of core flash memory cells'2003 6,590,811'Higher program VT and faster programming rates based on improved erase methods'2003 6,579,781'Elimination of n contact implant from flash technologies by replacement with standard double-diffused and n implants'2003 6,567,303'Charge injection'2003 6,512,701'Erase method for dual bit virtual ground flash'2003 6,493,266'Soft program and soft program verify of the core cells in flash memory array'2002 6,493,261'Single bit array edges'2002 6,456,533'Higher program VT and faster programming rates based on improved erase methods'2002 6,440,789'Photoresist spacer process simplification to eliminate the standard polysilicon or oxide spacer process for flash memory circuits'2002 6,442,074'Tailored erase method using higher program VT and higher negative gate erase'2002 6,385,093'I/O partitioning system and methodology to reduce band-to-band tunneling current during erase'2002 6,381,550'Method of utilizing fast chip erase to screen endurance rejects'2002 6,344,994'Data retention characteristics as a result of high temperature bake'2002 6,331,951'Method and system for embedded chip erase verification'2001 6,307,784'Negative gate erase'2001 6,277,690'Elimination of N+ implant from flash technologies by replacement with standard medium-doped-drain (Mdd) implant'2001 5,818,082'E.sup.2 PROM device having erase gate in oxide isolation region in shallow trench and method of manufacture thereof'1998 5,724,365'Method of utilizing redundancy testing to substitute for main array programming and AC speed reads'1998 5,656,521'Method of erasing UPROM transistors'1997

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1997–2006Patents assigned to ADVANCED MICRO DEVICES INC (35)· patent assignee history

1998–2010Based in San Jose, CA, US· patent location history

2004–2006Patents assigned to FASL LLC (4)· patent assignee history

2006–2015Patents assigned to SPANSION LLC (27)· patent assignee history

2009–2011Based in White Salmon, WA, US· patent location history

2010–2013Based in Husum, WA, US· patent location history

2011–2015Patents assigned to NANTERO INC (3)· patent assignee history

2011–2015Based in Lyle, WA, US· patent location history

2011–2015Based in Lacey, WA, US· patent location history

2012–2015Patents assigned to HAMILTON DARLENE (4)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
ADVANCED MICRO DEVICES INC	35	1997–2006
SPANSION LLC	27	2006–2015
FASL LLC	4	2004–2006
HAMILTON DARLENEself	4	2012–2015
NANTERO INC	3	2011–2015

Locations

Location	Patents	Span
San Jose, California, US	52	1998–2010
White Salmon, Washington, US	6	2009–2011
Lyle, Washington, US	4	2011–2015
Lacey, Washington, US	3	2011–2015
Husum, Washington, US	3	2010–2013