Inventor

VASANTH RANGANATHAN

Inventor

Overview

104→

Patents

2021–2026

Patent span

Physics

Primary field (CPC G)

Patents· 104 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Tprimary

G06TImage data processing or generation, in general33%

G06FElectric digital data processing29%

G06NComputing arrangements based on specific computational models16%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use10%

H03MCoding6%

G09GArrangements or circuits for control of indicating devices using static means to present variable information2%

H04NPictorial communication, e.g. television1%

G05DSystems for controlling or regulating non-electric variables1%

G06VImage or video recognition or understanding1%

G02BOptical elements, systems or apparatus1%

PatentTitleYear

12,585,590Broadcast asynchronous loads to shared local memory2026 12,579,072Graphics processor register file including a low energy portion and a high capacity portion2026 12,572,997Graphics processing unit processing and caching improvements2026 12,572,392Flexible partitioning of GPU resources2026 12,561,276Systems and methods for updating memory side caches in a multi-GPU configuration2026 12,554,674Multi-tile memory management2026 12,541,908Apparatus and method for throttling a ray tracing pipeline2026 12,504,989—2025 12,499,503Multi-render partitioning2025 12,493,922Graphics processing unit processing and caching improvements2025 12,462,328Coordination and increased utilization of graphics processors during inference2025 12,386,779Dynamic memory reconfiguration2025 12,361,600Systolic arithmetic on sparse data2025 12,346,798Dynamic precision for neural network compute operations2025 12,306,771Efficient data sharing for graphics data processing operations2025 12,299,766Providing native support for generic pointers in a graphics processing unit2025 12,293,431Sparse optimizations for a matrix accelerator architecture2025 12,242,414Data initialization techniques2025 12,236,498Generation and storage of compressed Z-planes in graphics processing2025 12,229,871Motion biased foveated renderer2025 12,217,053Instructions and logic to perform floating point and integer operations for machine learning2025 12,210,900Efficient thread group scheduling2025 12,210,477Systems and methods for improving cache efficiency and utilization2025 12,204,487Graphics processor data access and sharing2025 12,198,222Architecture for block sparse operations on a systolic array2025 12,190,118Data locality enhancement for graphics processing units2025 12,190,441Fragment compression for coarse pixel shading2025 12,182,062Multi-tile memory management2024 12,182,023Opportunistic late depth testing to prevent stalling for overlapping cache lines2024 12,182,035Systems and methods for cache optimization2024 12,164,952Barrier state save and restore for preemption in a graphics environment2024 12,153,541Cache structure and utilization2024 12,147,302Systems and methods for error detection and control for embedded memory and compute elements2024 12,141,094Systolic disaggregation within a matrix accelerator architecture2024 12,141,578Instructions and logic to perform floating point and integer operations for machine learning2024 12,124,383Systems and methods for cache optimization2024 12,124,852Instruction prefetch based on thread dispatch commands2024 12,099,461Multi-tile memory management2024 12,093,210Compression techniques2024 12,094,048Multi-tile graphics processor rendering2024 12,066,975Cache structure and utilization2024 12,056,059Systems and methods for cache optimization2024 12,045,658Stack access throttling for synchronous ray tracing2024 12,039,331Instructions and logic to perform floating point and integer operations for machine learning2024 12,032,496Efficient data sharing for graphics data processing operations2024 12,020,370Enhancing hierarchical depth buffer culling efficiency via mask accumulation2024 12,013,808Multi-tile architecture for graphics operations2024 12,001,209Barriers and synchronization for machine learning at autonomous machines2024 11,995,029Multi-tile memory management for detecting cross tile access providing multi-tile inference scaling and providing page migration2024 11,961,179Fragment compression for coarse pixel shading2024 11,954,062Dynamic memory reconfiguration2024 11,934,342Assistance for hardware prefetch in cache access2024 11,915,357Apparatus and method for throttling a ray tracing pipeline2024 11,892,950Data prefetching for graphics data processing2024 11,868,264Sector cache for compression2024 11,861,761Graphics processing unit processing and caching improvements2024 11,842,423Dot product operations on sparse matrix elements2023 11,809,905Local memory sharing between kernels2023 11,797,837Dynamic distributed training of machine learning models2023 11,762,662Instruction prefetch based on thread dispatch commands2023 11,755,501Efficient data sharing for graphics data processing operations2023 11,748,106Data operations and finite state machine for machine learning via bypass of computational tasks based on frequently-used data values2023 11,748,841Coordination and increased utilization of graphics processors during inference2023 11,748,606Dynamic precision for neural network compute operations2023 11,726,826Dynamic load balancing of compute assets among different compute contexts2023 11,726,793Data locality enhancement for graphics processing units2023 11,720,355Instructions and logic to perform floating point and integer operations for machine learning2023 11,676,239Sparse optimizations for a matrix accelerator architecture2023 11,670,044Fragment compression for coarse pixel shading2023 11,663,746Systolic arithmetic on sparse data2023 11,620,256Systems and methods for improving cache efficiency and utilization2023 11,615,584Hierarchical depth buffer back annotation2023 11,615,585Enhancing hierarchical depth buffer culling efficiency via mask accumulation2023 11,593,269Sector cache for compression2023 11,592,817Storage management for machine learning at autonomous machines2023 11,593,260Memory compression hashing mechanism2023 11,586,548Sector cache for compression2023 11,520,723Avoid thread switching in cache management2022 11,508,338Register spill/fill using shared local memory space2022 11,494,868Contextual configuration adjuster for graphics2022 11,494,187Message based general register file assembly2022 11,430,082Coordination and increased utilization of graphics processors during inference2022 11,409,658Data prefetching for graphics data processing2022 11,409,579Multiple independent synchonization named barrier within a thread group2022 11,393,211Hybrid graphics processor-field programmable gate array system2022 11,379,235Intelligent thread dispatch and vectorization of atomic operations2022 11,373,269Cache replacement mechanism2022 11,360,767Instructions and logic to perform floating point and integer operations for machine learning2022 11,360,808Efficient thread group scheduling2022 11,353,868Barriers and synchronization for machine learning at autonomous machines2022 11,354,848Motion biased foveated renderer2022 11,354,171De-centralized load-balancing at processors2022 11,321,262Interconnected systems fence mechanism2022 11,315,311Fragment compression for coarse pixel shading2022 11,295,481Fabric-based compression/decompression for internal data transfer2022 11,288,191Range based flushing mechanism2022 11,269,643Data operations and finite state machine for machine learning via bypass of computational tasks based on frequently-used data values2022 11,263,141Sector cache for compression2022 11,263,720Frequent data value compression for graphics processing units2022 11,250,539Low granularity coarse depth test efficiency enhancement2022 11,237,993Source synchronized signaling mechanism2022 11,176,083Switching crossbar for graphics pipeline2021 11,157,283Instruction prefetch based on thread dispatch commands2021 11,145,105Multi-tile graphics processor rendering2021

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2021–2026Patents assigned to INTEL CORP (104)· patent assignee history

2021–2026Based in US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	104	2021–2026

Locations

Location	Patents	Span
US	104	2021–2026