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Inventor

Eric N. Paton

Inventor
Morgan Hill, CA, US

Overview

74→
Patents
2000–2011
Patent span
Electricity
Primary field (CPC H)

Patents· 74 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices47%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1030%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
G01NInvestigating or analysing materials by determining their chemical or physical properties1%
H10BElectronic memory devices1%
Y10TTechnical subjects covered by former us classification1%
B24BMachines, devices, or processes for grinding or polishing1%
B82YSpecific uses or applications of nanostructures1%
C23CCoating metallic material1%
PatentTitleYear
7,863,175'Zero interface polysilicon to polysilicon gate for flash memory'20117,713,834'Method of forming isolation regions for integrated circuits'20107,648,886'Shallow trench isolation process'20107,456,062'Method of forming a semiconductor device'20087,422,961'Method of forming isolation regions for integrated circuits'20087,402,207'Method and apparatus for controlling the thickness of a selective epitaxial growth layer'20087,402,485'Method of forming a semiconductor device'20087,351,638'Scanning laser thermal annealing'20087,312,125'Fully depleted strained semiconductor on insulator transistor and method of making the same'20077,298,012'Shallow junction semiconductor'20077,256,141'Interface layer between dual polycrystalline silicon layers'20077,241,700'Methods for post offset spacer clean for improved selective epitaxy silicon growth'20077,211,489'Localized halo implant region formed using tilt pre-amorphization implant and laser thermal anneal'20077,091,097'End-of-range defect minimization in semiconductor device'20067,071,065'Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication'20067,033,916'Shallow junction semiconductor and method for the fabrication thereof'20066,966,235'Remote monitoring of critical parameters for calibration of manufacturing equipment and facilities'20056,967,160'Method of manufacturing semiconductor device having nickel silicide with reduced interface roughness'20056,962,857'Shallow trench isolation process using oxide deposition and anneal'20056,924,182'Strained silicon MOSFET having reduced leakage and method of its formation'20056,921,709'Front side seal to prevent germanium outgassing'20056,905,923'Offset spacer process for forming N-type transistors'20056,902,966'Low-temperature post-dopant activation process'20056,878,559'Measurement of lateral diffusion of diffused layers'20056,878,592'Selective epitaxy to improve silicidation'20056,873,051'Nickel silicide with reduced interface roughness'20056,867,428'Strained silicon NMOS having silicon source/drain extensions and method for its fabrication'20056,867,080'Polysilicon tilting to prevent geometry effects during laser thermal annealing'20056,858,503'Depletion to avoid cross contamination'20056,825,115'Post silicide laser thermal annealing to avoid dopant deactivation'20046,812,550'Wafer pattern variation of integrated circuit fabrication'20046,812,106'Reduced dopant deactivation of source/drain extensions using laser thermal annealing'20046,811,448'Pre-cleaning for silicidation in an SMOS process'20046,806,172'Physical vapor deposition of nickel'20046,797,614'Nickel alloy for SMOS process silicidation'20046,787,864'Mosfets incorporating nickel germanosilicided gate and methods for their formation'20046,784,506'Silicide process using high K-dielectrics'20046,780,789'Laser thermal oxidation to form ultra-thin gate oxide'20046,773,978'Methods for improved metal gate fabrication'20046,764,912'Passivation of nitride spacer'20046,746,944'Low nisi/si interface contact resistance with preamorphizing and laser thermal annealing'20046,743,689'Method of fabrication SOI devices with accurately defined monocrystalline source/drain extensions'20046,730,576'Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer'20046,727,176'Method of forming reliable Cu interconnects'20046,703,648'Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication'20046,703,277'Reducing agent for high-K gate dielectric parasitic interfacial layer'20046,689,688'Method and device using silicide contacts for semiconductor processing'20046,682,973'Formation of well-controlled thin SiO, SiN, SiON layer for multilayer high-K dielectric applications'20046,680,250'Formation of deep amorphous region to separate junction from end-of-range defects'20046,656,749'In-situ monitoring during laser thermal annealing'20036,646,307'MOSFET having a double gate'20036,638,861'Method of eliminating voids in W plugs'20036,632,729'Laser thermal annealing of high-k gate oxide layers'20036,605,513'Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing'20036,602,781'Metal silicide gate transistors'20036,562,718'Process for forming fully silicided gates'20036,559,051'Electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors'20036,555,439'Partial recrystallization of source/drain region before laser thermal annealing'20036,551,888'Tuning absorption levels during laser thermal annealing'20036,536,370'Elapsed time indicator for controlled environments and method of use'20036,514,859'Method of salicide formation with a double gate silicide'20036,475,874'Damascene NiSi metal gate high-k transistor'20026,465,334'Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors'20026,465,309'Silicide gate transistors'20026,458,679'Method of making silicide stop layer in a damascene semiconductor structure'20026,432,805'Co-deposition of nitrogen and metal for metal silicide formation'20026,399,467'Method of salicide formation'20026,387,786'Method of salicide formation by siliciding a gate area prior to siliciding a source and drain area'20026,368,950'Silicide gate transistors'20026,342,414'Damascene NiSi metal gate high-k transistor'20026,300,203'Electrolytic deposition of dielectric precursor materials for use in in-laid gate MOS transistors'20016,297,107'High dielectric constant materials as gate dielectrics'20016,297,159'Method and apparatus for chemical polishing using field responsive materials'20016,048,790'Metalorganic decomposition deposition of thin conductive films on integrated circuits using reducing ambient'2000

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2000–2008Patents assigned to ADVANCED MICRO DEVICES INC (69)· patent assignee history
2000–2011Based in Morgan Hill, CA, US· patent location history
2005Patents assigned to APPLIED MATERIALS INC (1)· patent assignee history
2005Patents assigned to PATON ERIC N (1)· patent assignee history
2007–2011Patents assigned to SPANSION LLC (2)· patent assignee history
2007Based in Morgan Hills, CA, US· patent location history
2010–2011Patents assigned to GLOBALFOUNDRIES INC (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
ADVANCED MICRO DEVICES INC692000–2008
GLOBALFOUNDRIES INC32010–2011
SPANSION LLC22007–2011
APPLIED MATERIALS INC12005
PATON ERIC Nself12005
Locations
LocationPatentsSpan
Morgan Hill, California, US732000–2011
Morgan Hills, California, US12007