Inventor
Yongping Fan
Inventor
Portland, OR, US
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Lprimary
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses33%
H01SDevices using the process of light amplification by stimulated emission of radiation [laser] to amplify or generate light7%
H03BGeneration of oscillations, directly or by frequency-changing, by circuits employing active elements which operate in a non-switching manner7%
H03KPulse technique7%
H10DInorganic electric semiconductor devices7%
H10HInorganic light-emitting semiconductor devices having potential barriers7%
B82YSpecific uses or applications of nanostructures5%
H03HImpedance networks, e.g. resonant circuits5%
H04LTransmission of digital information, e.g. telegraphic communication5%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
PatentTitleYear
10,976,673Levellable mask repository device202110,700,688Low power and low jitter phase locked loop with digital leakage compensation202010,574,243Apparatus and method for generating stable reference current20209,768,788'Phase-locked loop with lower power charge pump'20179,379,717'Apparatus to reduce power of a charge pump'20169,344,094'Temperature compensated PLL calibration'20169,281,824'Clock amplitude detection'20169,231,519'Temperature compensation for oscillator'20168,901,994'Digitally switched capacitor loop filter'20148,274,339'Automatic frequency control architecture with digital temperature compensation'20127,593,496'Phase interpolator'20097,583,151'VCO amplitude control'20097,501,904'Low power and duty cycle error free matched current phase locked loop'20097,501,869'Low power, low phase jitter, and duty cycle error insensitive clock receiver architecture and circuits for source synchronous digital data communication'20097,471,157'Low power/zero-offset charge pump circuits for DLLs and PLLs'20087,327,174'Fast locking mechanism for delay lock loops and phase lock loops'20087,202,715'Matched current delay cell and delay locked loop'20077,102,200'On-die termination resistor with analog compensation'20067,005,903'Output buffer with adjustment of signal transitions'20065,782,996'Graded compositions of II-VI semiconductors and devices utilizing same'19985,610,413'Group II-VI compound semiconductor light emitting devices and an ohmic contact therefor'19975,548,137'Group II-VI compound semiconductor light emitting devices and an ohmic contact therefor'1996Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1996–1997Patents assigned to RES CORP TECHNOLOGIES INC (2)· patent assignee history
1996–1997Based in West Lafayette, IN, US· patent location history
1998Based in Dallas, TX, US· patent location history
2006–2020Patents assigned to INTEL CORP (17)· patent assignee history
2006–2020Based in Portland, OR, US· patent location history
2012–2016Patents assigned to FAN YONGPING (4)· patent assignee history
2014Patents assigned to INTEL COPRORATION (1)· patent assignee history
2016Patents assigned to GOLTMAN GENNADY (1)· patent assignee history
2021Based in Shanghai, CN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 17 | 2006–2020 |
| FAN YONGPINGself | 4 | 2012–2016 |
| RES CORP TECHNOLOGIES INC | 2 | 1996–1997 |
| GOLTMAN GENNADY | 1 | 2016 |
| INTEL COPRORATION | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Portland, OR, US | 18 | 2006–2020 |
| West Lafayette, IN, US | 2 | 1996–1997 |
| Shanghai, CN | 1 | 2021 |
| Dallas, Texas, US | 1 | 1998 |