Inventor
Charan V. Surisetty
Inventor
Clifton Park, NY, US
Overview
Patents· 79 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices33%
H10DInorganic electric semiconductor devices32%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1015%
H10BElectronic memory devices3%
B82YSpecific uses or applications of nanostructures1%
Y02PClimate change mitigation technologies in the production or processing of goods0%
PatentTitleYear
11,038,055Method and structure of improving contact resistance for passive and long channel devices202111,037,875Forming dual metallization interconnect structures in single metallization level202111,031,337Forming dual metallization interconnect structures in single metallization level202110,937,861Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack202110,923,471Minimizing shorting between FinFET epitaxial regions202110,804,159Minimize middle-of-line contact line shorts202010,629,721Contact resistance reduction for advanced technology nodes202010,559,530Forming dual metallization interconnect structures in single metallization level202010,559,654Nanosheet isolation for bulk CMOS non-planar devices202010,490,454Minimize middle-of-line contact line shorts201910,396,200Method and structure of improving contact resistance for passive and long channel devices201910,381,458Semiconductor device replacement metal gate with gate cut last in RMG201910,361,203FET trench dipole formation201910,355,080Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack201910,347,628Simultaneously fabricating a high voltage transistor and a FinFET201910,347,632Forming spacer for trench epitaxial structures201910,347,633Spacer for trench epitaxial structures201910,276,569Minimizing shorting between FinFET epitaxial regions201910,256,296Middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack201910,249,624Semiconductor structure containing low-resistance source and drain contacts201910,243,044FinFETs with high quality source/drain structures201910,229,852Self-aligned low dielectric constant gate cap and a method of forming the same201910,177,240FinFET device formed by a replacement metal-gate method including a gate cut-last step201910,084,050Semiconductor device with low-K gate cap and self-aligned contact201810,074,569Minimize middle-of-line contact line shorts201810,043,904Method and structure of improving contact resistance for passive and long channel devices201810,020,306Spacer for trench epitaxial structures201810,014,220Self heating reduction for analog radio frequency (RF) device201810,014,295Self heating reduction for analog radio frequency (RF) device20189,985,024Minimizing shorting between FinFET epitaxial regions20189,972,620Preventing shorting between source and/or drain contacts and gate20189,966,374Semiconductor device with gate structures having low-K spacers on sidewalls and electrical contacts therebetween20189,953,976Effective device formation for advanced technology nodes with aggressive fin-pitch scaling20189,917,089'III-V semiconductor CMOS FinFET device'20189,905,463'Self-aligned low dielectric constant gate cap and a method of forming the same'20189,905,421'Improving channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devices'20189,899,378'Simultaneously fabricating a high voltage transistor and a finFET'20189,893,085'Integrated circuit (IC) with offset gate sidewall contacts and method of manufacture'20189,887,289'Method and structure of improving contact resistance for passive and long channel devices'20189,871,099'Nanosheet isolation for bulk CMOS non-planar devices'20189,852,951Minimizing shorting between FinFET epitaxial regions20179,799,654'FET trench dipole formation'20179,799,730'FINFETs with high quality source/drain structures'20179,773,905'Strained FinFET by epitaxial stressor independent of gate pitch'20179,768,173'Semiconductor structure containing low-resistance source and drain contacts'20179,728,626'Almost defect-free active channel region'20179,704,760'Integrated circuit (IC) with offset gate sidewall contacts and method of manufacture'20179,704,753'Minimizing shorting between FinFET epitaxial regions'20179,685,434'Inter-level dielectric layer in replacement metal gates and resistor fabrication'20179,685,340'Stable contact on one-sided gate tie-down structure'20179,673,101'Minimize middle-of-line contact line shorts'20179,647,113'Strained FinFET by epitaxial stressor independent of gate pitch'20179,627,322'Semiconductor device having reduced contact resistance'20179,607,898'Simultaneously fabricating a high voltage transistor and a finFET'20179,601,482'Economical and environmentally friendly chemical mechanical polishing for III-V compound semiconductor device fabrication'20179,595,592'Forming dual contact silicide using metal multi-layer and ion beam mixing'20179,589,827'Shallow trench isolation regions made from crystalline oxides'20179,564,370'Effective device formation for advanced technology nodes with aggressive fin-pitch scaling'20179,520,500'Self heating reduction for analog radio frequency (RF) device'20169,515,073'III-V semiconductor CMOS FinFET device'20169,508,816'Low resistance replacement metal gate structure'20169,484,401'Capacitance reduction for advanced technology nodes'20169,461,168'Channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devices'20169,443,853'Minimizing shorting between FinFET epitaxial regions'20169,431,486'Channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devices'20169,406,568'Semiconductor structure containing low-resistance source and drain contacts'20169,397,006'Co-integration of different fin pitches for logic and analog devices'20169,368,512'Double diamond shaped unmerged epitaxy for tall fins in tight pitch'20169,349,835'Methods for replacing gate sidewall materials with a low-k spacer'20169,337,094'Method of forming contact useful in replacement metal gate processing and related semiconductor structure'20169,305,923'Low resistance replacement metal gate structure'20169,293,576'Semiconductor device with low-k gate cap and self-aligned contact'20169,275,901'Semiconductor device having reduced contact resistance'20169,269,611'Integrated circuits having gate cap protection and methods of forming the same'20169,159,811'Growing buffer layers in bulk finFET structures'20159,087,796'Semiconductor fabrication method using stop layer'20159,059,164'Embedded interlevel dielectric barrier layers for replacement metal gate field effect transistors'20158,772,101'Methods of forming replacement gate structures on semiconductor devices and the resulting device'20148,728,927'Borderless contacts for semiconductor transistors'2014Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2014–2021Patents assigned to IBM (73)· patent assignee history
2014–2018Patents assigned to GLOBALFOUNDRIES INC (6)· patent assignee history
2014–2021Based in Clifton Park, NY, US· patent location history
2017Based in Cliffton Park, NY, US· patent location history
2021Patents assigned to TESSERA INC (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 73 | 2014–2021 |
| GLOBALFOUNDRIES INC | 6 | 2014–2018 |
| TESSERA INC | 2 | 2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| Clifton Park, New York, US | 78 | 2014–2021 |
| Cliffton Park, New York, US | 1 | 2017 |