Inventor

Mary E. Rothwell

Inventor

Ridgefield, CT, US

Overview

17→

Patents

2002–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 17 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary

H01LSemiconductor devices17%

B82YSpecific uses or applications of nanostructures15%

H10NElectric solid-state devices not otherwise provided for13%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%

G06NComputing arrangements based on specific computational models8%

H01PWaveguides6%

C08KUse of inorganic or non-macromolecular organic substances as compounding ingredients3%

C09JAdhesives3%

G02FOptical devices or arrangements for the control of light by modification of the optical properties of the media of the elements involved therein3%

PatentTitleYear

10,767,084Enhanced adhesive materials and processes for 3D applications2020 10,008,655Suspended superconducting qubits2018 9,994,741Enhanced adhesive materials and processes for 3D applications2018 9,716,219'Suspended superconducting qubits'2017 9,531,055'Removal of spurious microwave modes via flip-chip crossover'2016 9,520,547'Chip mode isolation and cross-talk reduction through buried metal layers and through-vias'2016 9,455,392'Method of fabricating a coplanar waveguide device including removal of spurious microwave modes via flip-chip crossover'2016 9,397,283'Chip mode isolation and cross-talk reduction through buried metal layers and through-vias'2016 9,219,298'Removal of spurious microwave modes via flip-chip crossover'2015 9,177,814'Suspended superconducting qubits'2015 9,064,717'Lock and key through-via method for wafer level 3D integration and structures produced thereby'2015 8,954,125'Low-loss superconducting devices'2015 8,093,099'Lock and key through-via method for wafer level 3D integration and structures produced'2012 7,855,455'Lock and key through-via method for wafer level 3 D integration and structures produced'2010 6,890,599'Self-assembled monolayer etch barrier for indium-tin-oxide useful in manufacturing thin film transistor-liquid crystal displays'2005 6,632,536'Self-assembled monolayer etch barrier for indium-tin-oxide useful in manufacturing thin film transistor-liquid crystal displays'2003 6,380,101'Method of forming patterned indium zinc oxide and indium tin oxide films via microcontact printing and uses thereof'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2020Patents assigned to IBM (16)· patent assignee history

2002–2018Based in Ridgefield, CT, US· patent location history

2012–2020Patents assigned to ROTHWELL MARY E (5)· patent assignee history

2012–2020Patents assigned to PURUSHOTHAMAN SAMPATH (4)· patent assignee history

2012–2015Based in Armonk, NY, US· patent location history

2018–2020Patents assigned to HEDRICK JAMES L (2)· patent assignee history

2018–2020Patents assigned to MILLER ROBERT DENNIS (2)· patent assignee history

2018–2020Based in Yorktown Heights, NY, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	16	2002–2020
ROTHWELL MARY Eself	5	2012–2020
PURUSHOTHAMAN SAMPATH	4	2012–2020
HEDRICK JAMES L	2	2018–2020
MILLER ROBERT DENNIS	2	2018–2020

Locations

Location	Patents	Span
Ridgefield, CT, US	13	2002–2018
Yorktown Heights, New York, US	2	2018–2020
Armonk, New York, US	2	2012–2015