LexDanaLexDanabeta
Inventor

Monte Manning

Inventor
Kuna, ID, US

Overview

157→
Patents
1991–2007
Patent span
Electricity
Primary field (CPC H)

Patents· 157 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices34%
H10BElectronic memory devices22%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests19%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
G11CStatic stores3%
PatentTitleYear
7,208,836'Integrated circuitry and a semiconductor processing method of forming a series of conductive lines'20077,148,134'Integrated circuitry and a semiconductor processing method of forming a series of conductive lines'20066,844,577'Thin film transistor'20056,767,785'Method of making a resistor, method of making a diode, and SRAM circuitry and other integrated circuitry'20046,759,285'Methods of forming transistors'20046,689,649'Methods of forming transistors'20046,611,059'Integrated circuitry conductive lines'20036,589,821'Methods of forming thin film transistors'20036,583,042'Semiconductor method of making electrical connection between an electrically conductive line and a node location, and integrated circuitry'20036,482,693'Methods of forming diodes'20026,479,332'Methods of forming integrated circuitry'20026,455,918'Integrated circuitry'20026,445,044'Apparatus improving latchup immunity in a dual-polysilicon gate'20026,432,764'Methods of forming resistors'20026,423,606'Semiconductor processing methods, methods of forming a resistor and methods of forming a diode'20026,420,219'Thin film transistors and method of forming thin film transistors'20026,391,734'Method of making a resistor, method of making a diode, and SRAM circuitry and other integrated circuitry'20026,376,287'Method of making field effect'20026,351,038'Integrated circuitry'20026,340,834'Method of making a resistor, method of making a diode, and SRAM circuitry and other integrated circuitry'20026,340,835'Method of making a resistor, method of making a diode, and SRAM circuitry and other integrated circuitry'20026,319,800'Static memory cell'20016,306,696'Methods of forming integrated circuitry methods of forming thin film transistors, integrated circuitry and thin film transistors'20016,284,648'Semiconductor processing method of forming a buried contact'20016,261,940'Semiconductor method of making electrical connection between an electrically conductive line and a node location, and integrated circuitry'20016,251,714'Method of making thin film field effect transistors'20016,242,781'Resistor constructions'20016,235,562'Method of making field effect transistors'20016,229,212'Integrated circuitry and thin film transistors'20016,225,172'Integrated circuitry and method of forming a field effect transistor'20016,214,652'Thin film transistors and method of forming thin film transistors'20016,207,512'Method and apparatus for improving latchup immunity in a dual-polysilicon gate process'20016,204,521'Thin film transistors'20016,200,839'Methods of forming thin film transistors'20016,200,835'Methods of forming conductive polysilicon lines and bottom gated thin film transistors, and conductive polysilicon lines and thin film transistors'20016,177,346'Integrated circuitry and method of forming a field effect transistor'20016,175,134'Thin film transistors'20016,166,398'Thin film transistors'20006,150,201'Methods of forming top-gated thin film field effect transistors'20006,147,406'Electrical connection between an electrically conductive line and a node location, and integrated circuitry'20006,141,239'Static memory cell'20006,137,146'Bipolar transistor and method of forming BiCMOS circuitry'20006,130,576'Thin film transistor redundancy structure'20006,117,716'Methods of forming BICMOS circuitry'20006,096,636'Methods of forming conductive lines'20006,093,596'Method of making a resistor, method of making a diode, and SRAM circuitry and other integrated circuitry'2000RE036735'Self-aligned low resistance buried contact process'20006,066,517'Method for forming a thin film transistor'20006,066,549'Semiconductor processing method of forming a conductive gate line and semiconductor processing method of making ohmic contact between a transistor gate line and a substrate diffusion region'20006,057,198'Semiconductor processing method of forming a buried contact'20006,048,781'Semiconductor processing method for providing large grain polysilicon films'20006,043,507'Thin film transistors and methods of making'20006,043,117'SRAM cell employing substantially vertically elongated pull-up resistors and methods of making, and resistor constructions and method of making'20006,040,221'Semiconductor processing methods of forming a buried contact, a conductive line, an electrical connection to a buried contact area, and a field effect transistor gate'20006,025,215'Method of making field effect transistors'20006,017,782'Thin film transistor and method of forming thin film transistors'20006,013,543'Methods of forming thin film transistors'20006,008,082'Method of making a resistor, method of making a diode, and SRAM circuitry and other integrated circuitry'19995,998,276'Methods of making a SRAM cell employing substantially vertically elongated pull-up resistors and methods of making resistor constructions'19995,985,702'Methods of forming conductive polysilicon lines and bottom gated thin film transistors, and conductive polysilicon lines and thin film transistors'19995,981,329'SRAM cell employing substantially vertically elongated pull-up resistors and methods of making, and resistor constructions and methods of making'19995,981,397'Integrated circuitry having a pair of adjacent conductive lines and method of forming'19995,978,258'MOS diode for use in a non-volatile memory cell background'19995,963,813'Integrated circuitry and method of forming a field effect transistor'19995,953,596'Methods of forming thin film transistors'19995,940,317'Static memory cell'19995,939,760'SRAM cell employing substantially vertically elongated pull-up resistors and methods of making, and resistor constructions and methods of making'19995,936,262'Thin film transistors'19995,932,490'Integrated circuitry having a pair of adjacent conductive lines and method of forming'19995,930,662'Method of making ohmic contact between a thin film polysilicon layer and a subsequently provided conductive layer and integrated circuitry'19995,930,615'Method of forming CMOS having simultaneous formation of halo regions of PMOS and part of source/drain of NMOS'19995,923,965'Thin film transistors and method of making'19995,909,631'Method of making ohmic contact between a thin film polysilicon layer and a subsequently provided conductive layer and integrated circuitry'19995,909,629'Semiconductor processing method of forming field oxide regions on a semiconductor substrate'19995,904,513'Method of forming thin film transistors'19995,895,766'Method of forming a field effect transistor'19995,888,874'Bipolar transistor and method of forming BiCMOS circuitry'19995,869,360'Method for forming a thin film transistor'19995,869,391'Semiconductor method of making electrical connection between an electrically conductive line and a node location, and integrated circuitry'19995,869,874'Field effect transistor with barrier layer'19995,858,821'Method of making thin film transistors'19995,856,703'Integrated circuitry having a pair of adjacent conductive lines'19995,847,406'Thin film field effect transistor'19985,843,814'Method of forming BiCMOS circuitry'19985,844,254'Planar thin film transistor structures'19985,834,970'Thin film transistor redundancy structure'19985,825,074'Method of making a resistor, method of making a diode, and SRAM circuitry and other integrated circuitry'19985,821,584'Thin film transistors comprising drain offset regions'19985,818,750'Static memory cell'19985,812,441'MOS diode for use in a non-volatile memory cell'19985,807,769'Methods of making thin film transistors'19985,804,838'Thin film transistors'19985,804,855'Thin film transistors'19985,801,423'Apparatus for improving latchup immunity in a dual polysilicon gate process'19985,801,087'Method of forming improved contacts from polysilicon to siliconor other polysilicon layers'19985,792,700'Semiconductor processing method for providing large grain polysilicon films'19985,780,326'Fully planarized thin film transistor (TFT) and process to fabricate same'19985,773,346'Semiconductor processing method of forming a buried contact'19985,759,881'Low cost well process'19985,757,052'Bipolar transistor and method of forming BiCMOS circuitry'19985,751,646'Redundancy elements using thin film transistors (TFTS)'19985,744,846'SRAM cell employing substantially vertically elongated pull-up resistors and methods of making, and resistor constructions and methods of making'19985,736,437'Method of fabricating a bottom and top gated thin film transistor having an electrical sidewall connection'19985,736,440'Semiconductor processing method of forming complementary NMOS and PMOS field effect transistors on a substrate'19985,729,055'Integrated circuitry having a thin film polysilicon layer in ohmic contact with a conductive layer'19985,700,727'Method of forming a thin film transistor'19975,700,733'Semiconductor processing methods of forming field oxide regions on a semiconductor substrate'19975,691,547'Planar thin film transistor structures'19975,691,565'Integrated circuitry having a pair of adjacent conductive lines'19975,683,930'SRAM cell employing substantially vertically elongated pull-up resistors and methods of making, and resistor constructions and methods of making'19975,681,778'Semiconductor processing method of forming a buried contact and conductive line'19975,677,241'Integrated circuitry having a pair of adjacent conductive lines and method of forming'19975,670,794'Thin film transistors'19975,670,399'Method of making thin film transistor with offset drain'19975,663,679'Thin film transistor redundancy structure'19975,661,045'Method for forming and tailoring the electrical characteristics of semiconductor devices'19975,658,807'Methods of forming conductive polysilicon lines and bottom gated thin film transistors'19975,659,183'Thin film transistor having a drain offset region'19975,650,655'Integrated circuitry having electrical interconnects'19975,644,540'Redundancy elements using thin film transistors (TFTs)'19975,616,934'Fully planarized thin film transistor (TFT) and process to fabricate same'19975,600,153'Conductive polysilicon lines and thin film transistors'19975,578,873'Integrated circuitry having a thin film polysilicon layer in ohmic contact with a conductive layer'19965,567,644'Method of making a resistor'19965,552,743'Thin film transistor redundancy structure'19965,548,132'Thin film transistor with large grain size DRW offset region and small grain size source and drain and channel regions'19965,541,137'Method of forming improved contacts from polysilicon to silicon or other polysilicon layers'19965,493,130'Integrated circuitry having an electrically conductive sidewall link positioned over and electrically interconnecting respective outer sidewalls of two conductive layers'19965,491,107'Semiconductor processing method for providing large grain polysilicon films'19965,434,103'Method of forming an electrical connection'19955,422,499'Sixteen megabit static random access memory (SRAM) cell'19955,420,061'Method for improving latchup immunity in a dual-polysilicon gate process'19955,411,909'Method of forming a planar thin film transistor'19955,405,788'Method for forming and tailoring the electrical characteristics of semiconductor devices'19955,392,245'Redundancy elements using thin film transistors (TFTs)'19955,390,143'Non-volatile static memory devices and operational methods'19955,385,854'Method of forming a self-aligned low density drain inverted thin film transistor'19955,348,899'Method of fabricating a bottom and top gated thin film transistor'19945,346,836'Process for forming low resistance contacts between silicide areas and upper level polysilicon interconnects'19945,334,862'Thin film transistor (TFT) loads formed in recessed plugs'19945,298,792'Integrated circuit device with bi-level contact landing pads'19945,292,676'Self-aligned low resistance buried contact process'19945,286,663'Methods for producing thin film transistor having a diode shunt'19945,275,965'Trench isolation using gated sidewalls'19945,266,523'Method of forming self-aligned contacts using the local oxidation of silicon'19935,246,876'Low cost polysilicon active P-channel load'19935,241,206'Self-aligned vertical intrinsic resistance'19935,232,865'Method of fabricating vertically integrated oxygen-implanted polysilicon resistor'19935,215,932'Self-aligned 3-dimensional PMOS devices without selective EPI'19935,214,295'Thin film field effect transistor, CMOS inverter, and methods of forming thin film field effect transistors and CMOS inverters'19935,212,399'Low cost polysilicon active p-channel load'19935,177,028'Trench isolation method having a double polysilicon gate formed on mesas'19935,177,030'Method of making self-aligned vertical intrinsic resistance'19935,175,127'Self-aligned interlayer contact process using a plasma etch of photoresist'19925,173,754'Integrated circuit device with gate in sidewall'19925,159,430'Vertically integrated oxygen-implanted polysilicon resistor'19925,055,426'Method for forming a multilevel interconnect structure on a semiconductor wafer'1991

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1991–2007Patents assigned to MICRON TECHNOLOGY INC (147)· patent assignee history
1991–2007Based in Kuna, ID, US· patent location history
1993–2005Based in Boise, ID, US· patent location history
1994–1996Patents assigned to MICRON SEMICONDUCTOR INC (9)· patent assignee history
1999Patents assigned to MICRON TEHNOLOGY INC (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MICRON TECHNOLOGY INC1471991–2007
MICRON SEMICONDUCTOR INC91994–1996
MICRON TEHNOLOGY INC11999
Locations
LocationPatentsSpan
Kuna, ID, US1011991–2007
Boise, ID, US561993–2005