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Inventor

Kho Liep Chok

Inventor
Singapore, SG

Overview

5→
Patents
2000–2011
Patent span
Electricity
Primary field (CPC H)

Patents· 5 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1083%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%
PatentTitleYear
7,989,338'Grain boundary blocking for stress migration and electromigration improvement in CU interconnects'20117,276,440'Method of fabrication of a die oxide ring'20077,224,060'Integrated circuit with protective moat'20076,339,027'Process for borderless stop in tin via formation'20026,127,238'Plasma enhanced chemical vapor deposited (PECVD) silicon nitride barrier layer for high density plasma chemical vapor deposited (HDP-CVD) dielectric layer'2000

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2000–2007Patents assigned to CHARTERED SEMICONDUCTOR MFG (4)· patent assignee history
2000–2007Based in Singapore, SG· patent location history
2011Patents assigned to GLOBALFOUNDRIES SG PTE LTD (1)· patent assignee history
2011Based in Cupertino, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
CHARTERED SEMICONDUCTOR MFG42000–2007
GLOBALFOUNDRIES SG PTE LTD12011
Locations
LocationPatentsSpan
Singapore, SG42000–2007
Cupertino, California, US12011