Inventor

Robert M. Wallace

Inventor
Richardson, TX, US

Overview

53→
Patents
1986–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 53 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1024%
H10DInorganic electric semiconductor devices23%
B82YSpecific uses or applications of nanostructures4%
G02BOptical elements, systems or apparatus4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
H01JElectric discharge tubes or discharge lamps3%
H10BElectronic memory devices3%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems2%
C23CCoating metallic material2%
F02BInternal-combustion piston engines2%
PatentTitleYear
11,081,590Metal oxide semiconductor field effect transistor with crystalline oxide layer on a III-V material202110,731,546Diffuser in wastegate turbine housings202010,475,930Method of forming crystalline oxides on III-V materials201910,100,785Compressor stage EGR injection20189,932,888Variable geometry turbocharger20189,812,568'Ionic barristor'20178,461,028'Synthesizing graphene from metal-carbon solutions using ion implantation'20138,309,438'Synthesizing graphene from metal-carbon solutions using ion implantation'20127,288,171'Method for using field emitter arrays in chemical and biological hazard mitigation and remediation'20077,115,461'High permittivity silicate gate dielectric'20067,030,038'Low temperature method for forming a thin, uniform oxide'20066,933,235'Method for removing contaminants on a substrate'20056,897,105'Method of forming metal oxide gate structures and capacitor electrodes'20056,841,439'High permittivity silicate gate dielectric'20056,784,507'Gate structure and method'20046,730,977'Lower temperature method for forming high quality silicon-nitrogen dielectrics'20046,624,944'Fluorinated coating for an optical element'20036,613,698'Lower temperature method for forming high quality silicon-nitrogen dielectrics'20036,552,388'Hafnium nitride gate dielectric'20036,468,856'High charge storage density integrated circuit capacitor'20026,436,801'Hafnium nitride gate dielectric'20026,420,729'Process to produce ultrathin crystalline silicon nitride on Si (111) for advanced gate dielectrics'20026,335,238'Integrated dielectric and method'20026,291,867'Zirconium and/or hafnium silicon-oxynitride gate dielectric'20016,291,866'Zirconium and/or hafnium oxynitride gate dielectric'20016,277,681'Process to produce ultrathin crystalline silicon nitride on Si(111) for advanced gate dielectrics'20016,274,510'Lower temperature method for forming high quality silicon-nitrogen dielectrics'20016,258,637'Method for thin film deposition on single-crystal semiconductor substrates'20016,245,606'Low temperature method for forming a thin, uniform layer of aluminum oxide'20016,159,829'Memory device using movement of protons'20006,150,242'Method of growing crystalline silicon overlayers on thin amorphous silicon oxide layers and forming by method a resonant tunneling diode'20006,143,634'Semiconductor process with deuterium predominance at high temperature'20006,140,243'Low temperature process for post-etch defluoridation of metals'20006,071,751'Deuterium sintering with rapid quenching'20006,040,230'Method of forming a nano-rugged silicon-containing layer'20006,024,801'Method of cleaning and treating a semiconductor device including a micromechanical device'20006,020,247'Method for thin film deposition on single-crystal semiconductor substrates'20006,020,243'Zirconium and/or hafnium silicon-oxynitride gate dielectric'20006,013,553'Zirconium and/or hafnium oxynitride gate dielectric'20005,881,505'Free-standing, prefabricated cremation memorial for cremation remains'19995,830,532'Method to produce ultrathin porous silicon-oxide layer'19985,689,151'Anode plate for flat panel display having integrated getter'19975,614,785'Anode plate for flat panel display having silicon getter'19975,610,438'Micro-mechanical device with non-evaporable getter'19975,606,177'Silicon oxide resonant tunneling diode structure'19975,523,878'Self-assembled monolayer coating for micro-mechanical devices'19965,520,563'Method of making a field emission device anode plate having an integrated getter'19965,512,374'PFPE coatings for micro-mechanical devices'19965,482,564'Method of unsticking components of micro-mechanical devices'19965,453,659'Anode plate for flat panel display having integrated getter'19955,352,330'Process for producing nanometer-size structures on surfaces using electron beam induced chemistry through electron stimulated desorption'19945,316,793'Directed effusive beam atomic layer epitaxy system and method'19944,567,432'Apparatus for testing integrated circuits'1986

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1986–2013Patents assigned to TEXAS INSTRUMENTS INC (42)· patent assignee history
1986–2000Based in Dallas, TX, US· patent location history
1997–2007Based in Richardson, TX, US· patent location history
1999Based in Las Vegas, NV, US· patent location history
2005–2007Patents assigned to UNIV NORTH TEXAS (2)· patent assignee history
2012–2021Patents assigned to UNIV TEXAS (5)· patent assignee history
2012–2021Based in Garland, TX, US· patent location history
2018–2020Patents assigned to BORGWARNER INC (3)· patent assignee history
2018–2020Based in Candler, NC, US· patent location history
2019–2021Patents assigned to SAMSUNG ELECTRONICS CO LTD (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TEXAS INSTRUMENTS INC421986–2013
UNIV TEXAS52012–2021
BORGWARNER INC32018–2020
SAMSUNG ELECTRONICS CO LTD22019–2021
UNIV NORTH TEXAS22005–2007
Locations
LocationPatentsSpan
Richardson, Texas, US321997–2007
Dallas, Texas, US121986–2000
Garland, Texas, US52012–2021
Candler, NC, US32018–2020
Las Vegas, NV, US11999