Inventor
Douglas T. Grider
Inventor
McKinney, TX, US
Overview
Patents· 51 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices39%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1025%
H01LSemiconductor devices11%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests7%
H10BElectronic memory devices6%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
G11CStatic stores4%
G01BMeasuring length, thickness or similar linear dimensions1%
G01NInvestigating or analysing materials by determining their chemical or physical properties1%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
PatentTitleYear
10,811,534Transistors with dual wells202010,622,073Integrated circuit including vertical capacitors202010,553,596Select gate self-aligned patterning in split-gate flash memory cell202010,446,563Partially disposed gate layer into the trenches201910,026,730Single mask level including a resistor and a through-gate implant20189,966,380Select gate self-aligned patterning in split-gate flash memory cell20189,881,795'Method of fabricating semiconductors'20189,761,581'Single mask level including a resistor and a through-gate implant'20179,490,143'Method of fabricating semiconductors'20169,461,060'Feed-forward bidirectional implanted split-gate flash memory cell'20169,431,248'High tilt angle plus twist drain extension implant for CHC lifetime improvement'20169,343,468'Feed-forward bidirectional implanted split-gate flash memory cell'20169,318,337'Three dimensional three semiconductor high-voltage capacitors'20169,177,802'High tilt angle plus twist drain extension implant for CHC lifetime improvement'20158,809,141'High performance CMOS transistors using PMD liner stress'20148,471,307'In-situ carbon doped e-SiGeCB stack for MOS transistor'20138,084,312'Nitrogen based implants for defect reduction in strained silicon'20118,084,787'PMD liner nitride films and fabrication methods for improved NMOS performance'20117,847,401'Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps'20107,670,892'Nitrogen based implants for defect reduction in strained silicon'20107,560,792'Reliable high voltage gate dielectric layers using a dual nitridation process'20097,553,718'Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps'20097,244,654'Drive current improvement from recessed SiGe incorporation close to gate'20077,226,834'PMD liner nitride films and fabrication methods for improved NMOS performance'20077,192,894'High performance CMOS transistors using PMD liner stress'20077,183,165'Reliable high voltage gate dielectric layers using a dual nitridation process'20076,933,248'Method for transistor gate dielectric layer with uniform nitrogen concentration'20056,737,333'Semiconductor device isolation structure and method of forming'20046,737,354'Method of CMOS source/drain extension with the PMOS implant spaced by poly oxide and cap oxide from the gates'20046,709,938'Source/drain extension fabrication process with direct implantation'20046,699,763'Disposable spacer technology for reduced cost CMOS processing'20046,645,840'Multi-layered polysilicon process'20036,632,747'Method of ammonia annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile'20036,632,718'Disposable spacer technology for reduced cost CMOS processing'20036,548,366'Method of two-step annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile'20036,503,846'Temperature spike for uniform nitridization of ultra-thin silicon dioxide layers in transistor gates'20036,326,281'Integrated circuit isolation'20016,242,295'Method of fabricating a shallow doped region for a shallow junction transistor'20016,136,654'Method of forming thin silicon nitride or silicon oxynitride gate dielectrics'20006,093,659'Selective area halogen doping to achieve dual gate oxide thickness on a wafer'20006,087,268'Method to reduce boron diffusion through gate oxide using sidewall spacers'20006,063,670'Gate fabrication processes for split-gate transistors'20006,030,874'Doped polysilicon to retard boron diffusion into and through thin gate dielectrics'20005,818,100'Product resulting from selective deposition of polysilicon over single crystal silicon substrate'19985,717,238'Substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant forming P-LDD region of a PMOS device'19985,646,073'Process for selective deposition of polysilicon over single crystal silicon substrate and resulting product'19975,585,286'Implantation of a semiconductor substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant subsequently implanted into the substrate to form P- LDD region of a PMOS device'19965,336,903'Selective deposition of doped silicon-germanium alloy on semiconductor substrate, and resulting structures'19945,242,847'Selective deposition of doped silion-germanium alloy on semiconductor substrate'19935,162,246'Selective germanium deposition on silicon and resulting structures'19925,089,872'Selective germanium deposition on silicon and resulting structures'1992Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1992–1994Patents assigned to UNIV NORTH CAROLINA STATE (4)· patent assignee history
1992–1993Based in Raleigh, NC, US· patent location history
1994–1998Based in Pleasanton, CA, US· patent location history
1996–1998Patents assigned to LSI LOGIC CORP (4)· patent assignee history
1996–2020Based in McKinney, TX, US· patent location history
2000–2020Patents assigned to TEXAS INSTRUMENTS INC (43)· patent assignee history
2011–2014Patents assigned to BU HAOWEN (4)· patent assignee history
2011–2014Patents assigned to GRIDER DOUGLAS T (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TEXAS INSTRUMENTS INC | 43 | 2000–2020 |
| BU HAOWEN | 4 | 2011–2014 |
| LSI LOGIC CORP | 4 | 1996–1998 |
| UNIV NORTH CAROLINA STATE | 4 | 1992–1994 |
| GRIDER DOUGLAS Tself | 3 | 2011–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| McKinney, Texas, US | 45 | 1996–2020 |
| Pleasanton, California, US | 3 | 1994–1998 |
| Raleigh, NC, US | 3 | 1992–1993 |