Inventor
Weidan Li
Inventor
San Jose, CA, US
Overview
Patents· 15 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1035%
C23CCoating metallic material13%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
G06FElectric digital data processing9%
H01LSemiconductor devices9%
H10DInorganic electric semiconductor devices9%
G01RMeasuring electric variables4%
G11CStatic stores4%
H03KPulse technique4%
PatentTitleYear
9,449,709'Volatile memory and one-time program (OTP) compatible memory cell and programming method'20168,946,890'Power/ground layout for chips'20158,921,938'Laterally diffused metal oxide semiconductor (LDMOS) device with overlapping wells'20147,321,254'On-chip automatic process variation, supply voltage variation, and temperature deviation (PVT) compensation method'20087,181,712'Method of optimizing critical path delay in an integrated circuit design'20077,000,163'Optimized buffering for JTAG boundary scan nets'20066,893,962'Low via resistance system'20056,807,656'Decoupling capacitance estimation and insertion flow for ASIC designs'20046,794,756'Integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal lines'20046,756,674'Low dielectric constant silicon oxide-based dielectric layer for integrated circuit structures having improved compatibility with via filler materials, and method of making same'20046,608,365'Low leakage PMOS on-chip decoupling capacitor cells compatible with standard CMOS cells'20036,569,751'Low via resistance system'20036,423,628'Method of forming integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal lines'20026,391,768'Process for CMP removal of excess trench or via filler metal which inhibits formation of concave regions on oxide surface of integrated circuit structure'20026,329,720'Tungsten local interconnect for silicon integrated circuit structures, and method of making same'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2008Patents assigned to LSI LOGIC CORP (12)· patent assignee history
2001–2015Based in San Jose, CA, US· patent location history
2014Patents assigned to MARVELL INT LTD (1)· patent assignee history
2015Patents assigned to CHENG CHUAN-CHENG (1)· patent assignee history
2015Patents assigned to HAN CHUNG CHYUNG (1)· patent assignee history
2015Patents assigned to LI WEIDAN (1)· patent assignee history
2016Based in San Diego, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| LSI LOGIC CORP | 12 | 2001–2008 |
| CHENG CHUAN-CHENG | 1 | 2015 |
| HAN CHUNG CHYUNG | 1 | 2015 |
| LI WEIDANself | 1 | 2015 |
| MARVELL INT LTD | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 14 | 2001–2015 |
| San Diego, California, US | 1 | 2016 |