Inventor

Wei Hwang

Inventor

Armonk, NY, US

Overview

1985–2019

Patent span

Electricity

Primary field (CPC H)

Patents· 59 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Bprimary

H10BElectronic memory devices23%

G11CStatic stores21%

H10DInorganic electric semiconductor devices15%

G06FElectric digital data processing13%

H03KPulse technique10%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests7%

G01RMeasuring electric variables4%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%

H10NElectric solid-state devices not otherwise provided for1%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h101%

PatentTitleYear

10,430,124Disk managing method and raid controller2019 10,198,395Port multiplier system and operation method2019 7,284,028'Comparator eliminating need for one\'s complement logic for signed numbers'2007 6,890,766'Dual-type thin-film field-effect transistors and applications'2005 6,620,659'Merged logic and memory combining thin film and bulk Si transistors'2003 6,492,227'Method for fabricating flash memory device using dual damascene process'2002 6,437,623'Data retention registers'2002 6,307,805'High performance semiconductor memory device with low power consumption'2001 6,285,050'Decoupling capacitor structure distributed above an integrated circuit and method for making same'2001 6,279,144'Provably correct storage arrays'2001 6,271,542'Merged logic and memory combining thin film and bulk Si transistors'2001 6,230,290'Method of self programmed built in self test'2001 6,219,822'Method and system for tuning of components for integrated circuits'2001 6,175,949'Method and system for selecting sizes of components for integrated circuits'2001 6,151,266'Asynchronous multiport register file with self resetting write operation'2000 6,108,798'Self programmed built in self test'2000 6,090,153'Multi-threshold-voltage differential cascode voltage switch (DCVS) circuits'2000 5,995,425'Design of provably correct storage arrays'1999 5,973,529'Pulse-to-static conversion latch with a self-timed control circuit'1999 5,939,898'Input isolation for self-resetting CMOS macros'1999 5,901,304'Emulating quasi-synchronous DRAM with asynchronous DRAM'1999 5,883,814'System-on-chip layout compilation'1999 5,875,125'X+2X adder with multi-bit generate/propagate circuit'1999 5,790,839'System integration of DRAM macros and logic cores in a single chip architecture'1998 5,780,335'Method of forming a buried-sidewall-strap two transistor one capacitor trench cell'1998 5,777,491'High-performance differential cascode voltage switch with pass gate logic elements'1998 5,617,047'Reset and pulse width control circuits for high-performance multi-port memories and register files'1997 5,571,743'Method of making buried-sidewall-strap two transistor one capacitor trench cell'1996 5,541,887'Multiple port cells with improved testability'1996 5,481,495'Cells and read-circuits for high-performance register files'1996 5,453,953'Bandgap voltage reference generator'1995 5,362,663'Method of forming double well substrate plate trench DRAM cell array'1994 5,359,552'Power supply tracking regulator for a memory array'1994 5,336,629'Folder Bitline DRAM having access transistors stacked above trench storage capacitors, each such transistor employing a planar semiconductor body which spans adjacent capacitors'1994 5,300,800'Low leakage substrate plate DRAM cell'1994 5,292,678'Forming a bit line configuration for semiconductor memory'1994 5,268,871'Power supply tracking regulator for a memory array'1993 5,253,202'Word line driver circuit for dynamic random access memories'1993 5,250,829'Double well substrate plate trench DRAM cell array'1993 5,214,603'Folded bitline, ultra-high density dynamic random access memory having access transistors stacked above trench storage capacitors'1993 5,185,719'High speed dynamic, random access memory with extended reset/precharge time'1993 5,170,243'Bit line configuration for semiconductor memory'1992 5,157,634'DRAM having extended refresh time'1992 5,144,165'CMOS off-chip driver circuits'1992 5,107,459'Stacked bit-line architecture for high density cross-point memory cell array'1992 5,075,571'PMOS wordline boost cricuit for DRAM'1991 5,064,777'Fabrication method for a double trench memory cell device'1991 5,034,787'Structure and fabrication method for a double trench memory cell device'1991 5,021,355'Method of fabricating cross-point lightly-doped drain-source trench transistor'1991 4,988,637'Method for fabricating a mesa transistor-trench capacitor memory cell structure'1991 4,954,854'Cross-point lightly-doped drain-source trench transistor and fabrication process therefor'1990 4,954,731'Wordline voltage boosting circuits for complementary MOSFET dynamic memories'1990 4,922,128'Boost clock circuit for driving redundant wordlines and sample wordlines'1990 4,881,105'Integrated trench-transistor structure and fabrication process'1989 4,833,516'High density memory cell structure having a vertical trench transistor self-aligned with a vertical trench capacitor and fabrication methods therefor'1989 4,816,884'High density vertical trench transistor and capacitor memory cell structure and fabrication method therefor'1989 4,763,180'Method and structure for a high density VMOS dynamic ram array'1988 4,754,433'Dynamic ram having multiplexed twin I/O line pairs'1988 4,532,698'Method of making ultrashort FET using oblique angle metal deposition and ion implantation'1985

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1985–2007Patents assigned to IBM (57)· patent assignee history

1985–2005Based in Armonk, NY, US· patent location history

1996Based in Westchester, NY, US· patent location history

2007Based in La Verne, CA, US· patent location history

2019Patents assigned to ASMEDIA TECH INC (2)· patent assignee history

2019Based in New Taipei, TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	57	1985–2007
ASMEDIA TECH INC	2	2019

Locations

Location	Patents	Span
Armonk, New York, US	55	1985–2005
New Taipei, TW	2	2019
La Verne, California, US	1	2007
Westchester, New York, US	1	1996