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Inventor

Steven Lee Gregor

Inventor
Endicott, NY, US

Overview

41→
Patents
1990–2020
Patent span
Physics
Primary field (CPC G)

Patents· 41 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing49%
G11CStatic stores42%
G01RMeasuring electric variables9%
PatentTitleYear
10,783,299Simulation event reduction and power control during MBIST through clock tree management202010,706,952Testing for memories during mission mode self-test202010,706,950Testing for memory error correction code logic202010,699,795System, method and computer-accessible medium for automated identification of embedded physical memories using shared test bus access in intellectual property cores202010,593,419Failing read count diagnostics for memory built-in self-test202010,541,043On demand data stream controller for programming and executing operations in an integrated circuit202010,504,607Multiple-channel, programmable fuse control unit201910,482,989Dynamic diagnostics analysis for memory built-in self-test201910,395,747Register-transfer level design engineering change order strategy201910,387,599Systems, methods, and computer-readable media utilizing improved data structures and design flow for programmable memory built-in self-test (PMBIST)201910,387,598Verifying results in simulation through simulation add-on to support visualization of selected memory contents in real time201910,319,459Customizable built-in self-test testplans for memory units201910,192,013Test logic at register transfer level in an integrated circuit design201910,095,822Memory built-in self-test logic in an integrated circuit design201810,007,489Automated method identifying physical memories within a core or macro integrated circuit design20189,865,362'Method and apparatus for testing error correction code (ECC) logic and physical memory onboard a manufactured integrated circuit (IC)'20189,640,280'Power domain aware insertion methods and designs for testing and repairing memory'20178,990,749'Method and apparatus for optimizing memory-built-in-self test'20158,719,761'Method and apparatus for optimizing memory-built-in-self test'20148,677,196'Low cost production testing for memory'20148,296,703'Fault modeling for state retention logic'20128,271,226'Testing state retention logic in low power systems'20127,168,005'Programable multi-port memory BIST with compact microcode'20077,032,144'Method and apparatus for testing multi-port memories'20067,003,704'Two-dimensional redundancy calculation'20066,907,554'Built-in self test system and method for two-dimensional memory redundancy allocation'20056,874,111'System initialization of microcode-based memory built-in self-test'20056,651,201'Programmable memory built-in self-test combining microcode and finite state machine self-test'20036,557,127'Method and apparatus for testing multi-port memories'20036,490,660'Method and apparatus for a configurable multiple level cache with coherency in a multiprocessor system'20026,161,208'Storage subsystem including an error correcting cache and means for performing memory to memory transfers'20006,115,795'Method and apparatus for configurable multiple level cache with coherency in a multiprocessor system'20005,909,694'Multiway associative external microprocessor cache'19995,860,138'Processor with compiler-allocated, variable length intermediate storage'19995,553,305'System for synchronizing execution by a processing element of threads within a process using a state indicator'19965,450,563'Storage protection keys in two level cache system'19955,313,613'Execution of storage-immediate and storage-storage instructions within cache buffer storage'19945,276,848'Shared two level cache including apparatus for maintaining storage consistency'19945,226,169'System for execution of storage-immediate and storage-storage instructions within cache buffer storage'19935,023,776'Store queue for a tightly coupled multiple processor configuration with two-level cache buffer storage'19914,924,466'Direct hardware error identification method and apparatus for error recovery in pipelined processing areas of a computer system'1990

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1990–2006Patents assigned to IBM (16)· patent assignee history
1990–2007Based in Endicott, NY, US· patent location history
2003–2020Patents assigned to CADENCE DESIGN SYSTEMS INC (25)· patent assignee history
2012–2015Patents assigned to ARORA PUNEET (4)· patent assignee history
2012Patents assigned to CHAKRAVADHANULA KRISHNA (2)· patent assignee history
2012–2020Based in Owego, NY, US· patent location history
2014–2015Patents assigned to CARD NORMAN (2)· patent assignee history
2018–2020Based in Oswego, NY, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
CADENCE DESIGN SYSTEMS INC252003–2020
IBM161990–2006
ARORA PUNEET42012–2015
CARD NORMAN22014–2015
CHAKRAVADHANULA KRISHNA22012
Locations
LocationPatentsSpan
Endicott, New York, US191990–2007
Oswego, New York, US122018–2020
Owego, New York, US102012–2020