Inventor
Nicholas A. Lanzillo
Inventor
Troy, NY, US
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices33%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1018%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
H10NElectric solid-state devices not otherwise provided for12%
H10BElectronic memory devices9%
G01RMeasuring electric variables5%
G11CStatic stores5%
G06NComputing arrangements based on specific computational models2%
H01FMagnets2%
PatentTitleYear
11,062,943Top via interconnects with wrap around liner202111,049,744Optimizing semiconductor binning by feed-forward process adjustment202110,978,393Hybrid dielectric scheme for varying liner thickness and manganese concentration202110,978,342Interconnect with self-forming wrap-all-around barrier layer202110,978,343Interconnect structure having fully aligned vias202110,886,166Dielectric surface modification in sub-40nm pitch interconnect patterning202110,830,841Magnetic tunnel junction performance monitoring based on magnetic field coupling202010,796,833Magnetic tunnel junction with low series resistance202010,770,511Structures and methods for embedded magnetic random access memory (MRAM) fabrication202010,746,782Accelerated wafer testing using non-destructive and localized stress202010,739,397Accelerated wafer testing using non-destructive and localized stress202010,741,751Fully aligned semiconductor device with a skip-level via202010,727,124Structure and method for forming fully-aligned trench with an up-via integration scheme202010,720,567Prevention of switching of spins in magnetic tunnel junctions by on-chip parasitic magnetic shield202010,553,789Fully aligned semiconductor device with a skip-level via202010,319,629Skip via for metal interconnects201910,256,191Hybrid dielectric scheme for varying liner thickness and manganese concentration201910,243,020Structures and methods for embedded magnetic random access memory (MRAM) fabrication201910,211,155Reducing metallic interconnect resistivity through application of mechanical strain20199,985,199Prevention of switching of spins in magnetic tunnel junctions by on-chip parasitic magnetic shield20189,941,211Reducing metallic interconnect resistivity through application of mechanical strain2018Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2018–2021Patents assigned to IBM (21)· patent assignee history
2018–2021Based in Troy, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 21 | 2018–2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| Troy, New York, US | 21 | 2018–2021 |