Inventor

Yasuyuki Nozuyama

Inventor

Tokyo, JP

Overview

1990–2015

Patent span

Physics

Primary field (CPC G)

Patents· 39 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G01Rprimary

G01RMeasuring electric variables46%

G06FElectric digital data processing32%

G11CStatic stores11%

H03KPulse technique7%

H10DInorganic electric semiconductor devices2%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%

PatentTitleYear

9,075,946'Method for designing semiconductor integrated circuit'2015 8,886,487'Bridge fault removal apparatus, bridge fault removal method, and computer readable medium comprising computer program code for removing bridge fault'2014 8,508,249'Semiconductor integrated circuit and method for designing the same'2013 8,185,863'Delay fault test quality calculation apparatus, delay fault test quality calculation method, and delay fault test pattern generation apparatus'2012 8,082,534'Apparatus and method for calculating fault coverage, and fault detection method'2011 8,051,403'Delay fault test quality calculation apparatus, delay fault test quality calculation method, and delay fault test pattern generation apparatus'2011 7,966,138'Apparatus for creating test pattern and calculating fault coverage or the like and method for creating test pattern and calculating fault coverage or the like'2011 7,913,143'Test quality evaluating and improving system for semiconductor integrated circuit and test quality evaluation and improvement method for semiconductor integrated circuit'2011 7,406,645'Test pattern generating apparatus, method for automatically generating test patterns and computer program product for executing an application for a test pattern generating apparatus'2008 7,392,146'Fault list and test pattern generating apparatus and method, fault list generating and fault coverage calculating apparatus and method'2008 7,308,660'Calculation system of fault coverage and calculation method of the same'2007 7,283,918'Apparatus for analyzing fault of semiconductor integrated circuit, method for the same, and computer readable medium for the same'2007 7,162,674'Apparatus for selecting test patterns for logic circuit, computer implemented method for selecting test patterns, and computer program product for controlling a computer system so as to select test patterns'2007 7,139,956'Semiconductor integrated circuit device and test method thereof'2006 7,096,140'Test system, test method and test program for an integrated circuit by IDDQ testing'2006 7,093,216'Apparatus connectable to a computer network for circuit design verification, computer implemented method for circuit design verification, and computer program product for controlling a computer system so as to verify circuit designs'2006 7,082,559'Semiconductor integrated circuit device and test method thereof'2006 6,834,368'Semiconductor integrated circuit including a test facilitation circuit for functional blocks intellectual properties and automatic insertion method of the same test facilitation circuit'2004 6,766,473'Test pattern selection apparatus for selecting test pattern from a plurality of check patterns'2004 6,567,946'Evaluation device of weighted fault coverage and evaluation method of the same'2003 6,223,312'Test-facilitating circuit for information processing devices'2001 6,151,694'Method of evaluating fault coverage'2000 6,148,434'Apparatus and method for minimizing the delay times in a semiconductor device'2000 6,101,623'Current reduction circuit for testing purpose'2000 5,867,409'Linear feedback shift register'1999 5,862,359'Data transfer bus including divisional buses connectable by bus switch circuit'1999 5,821,786'Semiconductor integrated circuit having function for evaluating AC performance'1998 5,677,916'Semiconductor integrated circuit and its application device'1997 5,631,910'Information processing system provided with self-diagnosing circuit and the self-diagnosing method therefor'1997 5,592,494'Current reduction circuit for testing purpose'1997 5,588,006'Logic circuit having a control signal switching logic function and having a testing arrangement'1996 5,515,517'Data processing device with test circuit'1996 5,504,755'Testable programmable logic array'1996 5,398,250'Circuit for testing circuit blocks controlled by microinstructions'1995 5,202,978'Self-test circuit of information processor'1993 5,189,675'Self-diagnostic circuit for logic circuit block'1993 5,184,067'Signature compression circuit'1993 4,965,511'Test circuit for logic ICS'1990 4,902,918'Programmable logic arrays with each array column divided into a plurality of series connections of FETs'1990

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1990–2015Patents assigned to TOSHIBA KK (38)· patent assignee history

1990–2015Based in Tokyo, JP· patent location history

1990Based in Meguro-ku, JP· patent location history

2003–2012Based in Inagi, JP· patent location history

2007–2011Based in Inashiro, JP· patent location history

2011–2014Patents assigned to NOZUYAMA YASUYUKI (4)· patent assignee history

2011Patents assigned to FUJITSU SEMICONDOCTOR LTD (1)· patent assignee history

2012Patents assigned to FUJITSU SEMICONDUCTOR LTD (1)· patent assignee history

2012Patents assigned to TAKATORI ATSUO (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TOSHIBA KK	38	1990–2015
NOZUYAMA YASUYUKIself	4	2011–2014
FUJITSU SEMICONDOCTOR LTD	1	2011
FUJITSU SEMICONDUCTOR LTD	1	2012
TAKATORI ATSUO	1	2012

Locations

Location	Patents	Span
Tokyo, JP	29	1990–2015
Inagi, JP	7	2003–2012
Inashiro, JP	2	2007–2011
Meguro-ku, JP	1	1990