Inventor
Chuan Hu
Inventor
Chandler, AZ, US
Overview
Patents· 59 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1036%
H01LSemiconductor devices18%
H05KPrinted circuits10%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h109%
Y10TTechnical subjects covered by former us classification9%
H01QAntennas, i.e. radio aerials3%
B23KSoldering or unsoldering2%
G06FElectric digital data processing2%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
B32BLayered products, i.e. products built-up of strata of flat or non-flat, e.g. cellular or honeycomb, form1%
PatentTitleYear
11,010,065Read retry method for solid state storage device202110,867,959Integrated circuit packaging method and integrated packaged circuit202010,867,961Single layer low cost wafer level packaging for SFF SiP202010,847,496Chip wiring method and structure202010,615,151Integrated circuit multichip stacked packaging structure and method202010,535,634Multi-layer package202010,468,367Solder in cavity interconnection structures201910,381,288Packaged semiconductor die and CTE-engineering die pair201910,256,211Multi-chip-module semiconductor chip package having dense package wiring201910,122,089Magnetic nanocomposite materials and passive components formed therewith201810,096,535Packaged semiconductor die and CTE-engineering die pair201810,014,277Single layer low cost wafer level packaging for SFF SiP20189,951,410Infrared surface light source generating device and method of manufacturing same20189,942,980Wavy interconnect for bendable and stretchable devices20189,930,793'Electric circuit on flexible substrate'20189,848,490Solder in cavity interconnection technology20179,761,514'Substrate for integrated circuit devices including multi-layer glass core and methods of making the same'20179,741,645'Dense interconnect with solder cap (DISC) formation with laser ablation and resulting semiconductor structures and packages'20179,685,390'Microelectronic package having non-coplanar, encapsulated microelectronic devices and a bumpless build-up layer'20179,673,131'Integrated circuit package assemblies including a glass solder mask layer'20179,659,885'Semiconductor device with pre-molding chip bonding'20179,543,197'Package with dielectric or anisotropic conductive (ACF) buildup layer'20179,530,747'Solder in cavity interconnection structures'20169,508,675'Microelectronic package having direct contact heat spreader and method of manufacturing same'20169,461,355'Method apparatus and material for radio frequency passives and antennas'20169,420,707'Substrate for integrated circuit devices including multi-layer glass core and methods of making the same'20169,281,292'Single layer low cost wafer level packaging for SFF SiP'20169,072,187'Off-plane conductive line interconnects in microelectronic devices'20159,006,890'Solder in cavity interconnection structures'20158,936,967'Solder in cavity interconnection structures'20158,872,355'Semiconductor device with pre-molding chip bonding'20148,663,485'Method of manufacturing plastic metallized three-dimensional circuit'20148,541,876'Microelectronic package having direct contact heat spreader and method of manufacturing same'20138,424,748'Solder in cavity interconnection technology'20138,080,870'Die-warpage compensation structures for thinned-die devices, and methods of assembling same'20117,888,183'Thinned die integrated circuit package'20117,882,624'Method of forming electronic package having fluid-conducting channel'20117,713,839'Diamond substrate formation for electronic assemblies'20107,682,876'Electronic assemblies having a low processing temperature'20107,646,093'Thermal management of dies on a secondary side of a package'20107,626,251'Microelectronic die assembly having thermally conductive element at a backside thereof and method of making same'20097,560,640'Densely packed thermoelectric cooler'20097,531,429'Methods and apparatuses for manufacturing ultra thin device layers for integrated circuit devices'20097,495,630'Feed point adjustable planar antenna'20097,476,568'Wafer-level assembly of heat spreaders for dual IHS packages'20097,420,273'Thinned die integrated circuit package'20087,397,119'Wafer-level diamond spreader'20087,382,323'Micro chip antenna'20087,319,048'Electronic assemblies having a low processing temperature'20087,301,461'SOC for integrating micro-antenna'20077,279,796'Microelectronic die having a thermoelectric module'20077,259,965'Integrated circuit coolant microchannel assembly with targeted channel configuration'20077,126,822'Electronic packages, assemblies, and systems with fluid cooling'20067,095,111'Package with integrated wick layer and method for heat removal'20067,091,108'Methods and apparatuses for manufacturing ultra thin device layers for integrated circuit devices'20067,038,316'Bumpless die and heat spreader lid module bonded to bumped die carrier'20067,012,011'Wafer-level diamond spreader'20067,009,289'Fluxless die-to-heat spreader bonding using thermal interface material'20066,833,289'Fluxless die-to-heat spreader bonding using thermal interface material'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2020Patents assigned to INTEL CORP (50)· patent assignee history
2004–2020Based in Chandler, AZ, US· patent location history
2007–2009Patents assigned to CHANT SINCERE CO LTD (3)· patent assignee history
2007–2021Based in Taipei, TW· patent location history
2009Based in Hsichih, TW· patent location history
2011–2018Patents assigned to HU CHUAN (15)· patent assignee history
2015–2016Patents assigned to LIFF SHAWNA M (3)· patent assignee history
2018Based in New Taipei, TW· patent location history
2020Patents assigned to SHENZHEN XIUYUAN ELECTRONIC TECH CO LTD (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 50 | 2004–2020 |
| HU CHUANself | 15 | 2011–2018 |
| CHANT SINCERE CO LTD | 3 | 2007–2009 |
| LIFF SHAWNA M | 3 | 2015–2016 |
| SHENZHEN XIUYUAN ELECTRONIC TECH CO LTD | 3 | 2020 |
Locations
| Location | Patents | Span |
|---|---|---|
| Chandler, AZ, US | 53 | 2004–2020 |
| Taipei, TW | 4 | 2007–2021 |
| New Taipei, TW | 1 | 2018 |
| Hsichih, TW | 1 | 2009 |