Inventor
Joodong Park
Inventor
Portland, OR, US
Overview
Patents· 28 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices37%
H01LSemiconductor devices33%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%
H10BElectronic memory devices5%
B82YSpecific uses or applications of nanostructures1%
PatentTitleYear
10,847,544High voltage three-dimensional devices having dielectric liners202010,784,378Ultra-scaled fin pitch having dual gate dielectrics202010,692,888High voltage three-dimensional devices having dielectric liners202010,658,361Methods of integrating multiple gate dielectric transistors on a tri-gate (FINFET) process202010,559,688Transistor with thermal performance boost202010,535,747Transistor with dual-gate spacer202010,431,661Transistor with inner-gate spacer201910,355,093Non-planar semiconductor device having omega-fin with doped sub-fin region and method to fabricate same201910,340,220Compound lateral resistor structures for integrated circuitry201910,304,681Dual height glass for finFET doping201910,263,112Vertical non-planar semiconductor device for system-on-chip (SoC) applications201910,204,999Transistor with airgap spacer201910,096,599Methods of integrating multiple gate dielectric transistors on a tri-gate (finFET) process20189,972,642High voltage three-dimensional devices having dielectric liners20189,881,927'CMOS-compatible polycide fuse structure and method of fabricating same'20189,806,095'High voltage three-dimensional devices having dielectric liners'20179,786,783'Transistor architecture having extended recessed spacer and source/drain regions and method of making same'20179,780,217'Non-planar semiconductor device having self-aligned fin with top blocking layer'20179,748,252'Antifuse element utilizing non-planar topology'20179,741,721'Low leakage non-planar access transistor for embedded dynamic random access memory (eDRAM)'20179,570,467'High voltage three-dimensional devices having dielectric liners'20179,520,494'Vertical non-planar semiconductor device for system-on-chip (SoC) applications'20169,159,734'Antifuse element utilizing non-planar topology'20158,981,481'High voltage three-dimensional devices having dielectric liners'20158,889,508'Precision resistor for non-planar semiconductor device architecture'20148,796,772'Precision resistor for non-planar semiconductor device architecture'20148,669,617'Multi-gate transistors'20147,691,718'Dual layer hard mask for block salicide poly resistor (BSR) patterning'2010Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2010–2020Patents assigned to INTEL CORP (28)· patent assignee history
2010–2020Based in Portland, OR, US· patent location history
2014–2020Patents assigned to HAFEZ WALID M (7)· patent assignee history
2014–2020Patents assigned to PARK JOODONG (7)· patent assignee history
2014–2020Patents assigned to TSAI CURTIS (7)· patent assignee history
2014–2017Patents assigned to JAN CHIA-HONG (6)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 28 | 2010–2020 |
| HAFEZ WALID M | 7 | 2014–2020 |
| PARK JOODONGself | 7 | 2014–2020 |
| TSAI CURTIS | 7 | 2014–2020 |
| JAN CHIA-HONG | 6 | 2014–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Portland, OR, US | 28 | 2010–2020 |