Inventor

John K. Walton

Inventor

Mendon, MA, US

Overview

1998–2013

Patent span

Physics

Primary field (CPC G)

Patents· 49 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing70%

G11CStatic stores10%

H04LTransmission of digital information, e.g. telegraphic communication10%

H05KPrinted circuits3%

H03MCoding2%

LOC122%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%

Y02PClimate change mitigation technologies in the production or processing of goods2%

PatentTitleYear

8,554,943'Method and system for reducing packet latency in networks with both low latency and high bandwidths requirements'2013 7,821,922'Fault isolation and handling in a packet switching network'2010 7,774,631'Method and system for minimizing power consumption in a multiprocessor data storage system'2010 7,552,282'Method, computer readable medium, and data storage system for selective data replication of cached data'2009 D0587182'Anchor'2009 7,454,536'Data system having a virtual queue'2008 7,437,425'Data storage system having shared resource'2008 7,272,668'System having backplane performance capability selection logic'2007 7,124,245'Data storage system having cache memory manager with packet switching network'2006 7,020,754'Method and system for maintaining data integrity using dual write operations'2006 7,010,740'Data storage system having no-operation command'2006 7,007,194'Data storage system having point-to-point configuration'2006 6,988,152'Data storage system'2006 6,973,551'Data storage system having atomic memory operation'2005 6,957,285'Data storage system'2005 6,910,145'Data transmission across asynchronous clock domains'2005 6,904,556'Systems and methods which utilize parity sets'2005 6,886,116'Data storage system adapted to validate error detection logic used in such system'2005 6,882,620'Token exchange system with fault protection'2005 6,883,072'Memory system and method of using same'2005 6,877,061'Data storage system having dummy printed circuit boards'2005 6,868,516'Method for validating write data to a memory'2005 6,804,794'Error condition handling'2004 6,779,150'CRC error detection system and method'2004 6,687,797'Arbitration system and method'2004 6,636,933'Data storage system having crossbar switch with multi-staged routing'2003 6,609,185'Data storage system having majority gate filter'2003 6,604,176'Data storage system having plural fault domains'2003 6,594,739'Memory system and method of using same'2003 6,578,126'Memory system and method of using same'2003 6,567,903'Data storage system having master/slave addressable memories'2003 6,505,321'Fault tolerant parity generation'2003 6,502,149'Plural bus data storage system'2002 6,397,281'Bus arbitration system'2002 6,389,494'System for interfacing a data storage system to a host utilizing a plurality of busses for carrying end-user data and a separate bus for carrying interface state data'2002 6,347,365'Data storage system having an memory responsive to clock pulses produced on a bus and clock pulses produced by an internal clock'2002 6,249,878'Data storage system'2001 6,195,770'Data storage system'2001 6,145,042'Timing protocol for a data storage system'2000 6,138,195'Method and apparatus for hot-plugging circuit boards having low voltage logic parts into a higher voltage backplane'2000 5,959,932'Method and apparatus for detecting errors in the writing of data to a memory'1999 5,954,838'Data storage system having row/column address parity checking'1999 5,953,265'Memory having error detection and correction'1999 5,951,693'Data storage system having data reconstruction'1999 5,943,287'Fault tolerant memory system'1999 5,936,844'Memory system printed circuit board'1999 5,886,930'Bit interleaving in a memory which uses multi-bit DRAMs'1999 5,850,528'Bus timing protocol for a data storage system'1998 5,822,777'Dual bus data storage system having an addressable memory with timer controller fault detection of data transfer between the memory and the buses'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2013Patents assigned to EMC CORP (48)· patent assignee history

1998–2005Based in Hopedale, MA, US· patent location history

1999–2013Based in Mendon, MA, US· patent location history

2009Patents assigned to WAVE STAKE LLC (1)· patent assignee history

2009Based in Chippewa Falls, WI, US· patent location history

2013Patents assigned to CHILTON KENDELL (1)· patent assignee history

2013Patents assigned to WALTON JOHN K (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
EMC CORP	48	1998–2013
CHILTON KENDELL	1	2013
WALTON JOHN Kself	1	2013
WAVE STAKE LLC	1	2009

Locations

Location	Patents	Span
Mendon, Massachusetts, US	42	1999–2013
Hopedale, Massachusetts, US	6	1998–2005
Chippewa Falls, WI, US	1	2009