Inventor
Yasuyuki Morishita
Inventor
Tokyo, JP
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices63%
H01LSemiconductor devices14%
H03FAmplifiers9%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
A01NPreservation of bodies of humans or animals or plants or parts thereof3%
H02HEmergency protective circuit arrangements3%
PatentTitleYear
10,790,277Semiconductor device202010,424,920Semiconductor device201910,256,228Semiconductor device201910,111,423Microbial pesticide composition of dried 20189,548,296'Semiconductor electrostatic protection circuit device'20178,785,972'Semiconductor electrostatic protection circuit device'20148,493,698'Electrostatic discharge protection circuit'20138,045,304'Semiconductor circuit including electrostatic discharge circuit having protection element and trigger transistor'20117,495,265'ESD protection circuit with SCR structure for semiconductor device'20097,456,440'Electrostatic protection device'20087,339,771'Electrostatic protection circuit'20087,187,037'ESD protection devices with SCR structures for semiconductor integrated circuits'20077,064,392'Semiconductor device'20066,894,321'ESD protection circuit with plural thyristors'20056,759,716'Input/output protection device for a semiconductor integrated circuit'20046,680,833'Input-output protection device for semiconductor integrated circuit'20046,600,210'Semiconductor device and method of manufacturing the same'20036,545,321'ESD protection circuit for a semiconductor integrated circuit'20036,483,365'Semiconductor device'20026,472,923'Semiconductor device'20026,455,895'Overvoltage protector having same gate thickness as the protected integrated circuit'20026,445,040'Lateral bipolar type input/output protection device'20026,426,665'Semiconductor device'20025,529,956'Multi-layer wiring structure in semiconductor device and method for manufacturing the same'1996Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1996–2002Patents assigned to NEC CORP (6)· patent assignee history
1996–2019Based in Tokyo, JP· patent location history
2003–2009Patents assigned to NEC ELECTRONICS CORP (10)· patent assignee history
2005–2017Based in Kanagawa, JP· patent location history
2011–2020Patents assigned to RENESAS ELECTRONICS CORP (7)· patent assignee history
2013Patents assigned to MORISHITA YASUYUKI (1)· patent assignee history
2018Patents assigned to IDEMITSU KOSAN CO (1)· patent assignee history
2018Based in Ibaraki, JP· patent location history
2019–2020Based in Kodaira, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NEC ELECTRONICS CORP | 10 | 2003–2009 |
| RENESAS ELECTRONICS CORP | 7 | 2011–2020 |
| NEC CORP | 6 | 1996–2002 |
| IDEMITSU KOSAN CO | 1 | 2018 |
| MORISHITA YASUYUKIself | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tokyo, JP | 12 | 1996–2019 |
| Kanagawa, JP | 9 | 2005–2017 |
| Kodaira, JP | 2 | 2019–2020 |
| Ibaraki, JP | 1 | 2018 |