Inventor
Ming-Yi Lee
Inventor
Fremont, CA, US
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices21%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%
G11CStatic stores9%
G01NInvestigating or analysing materials by determining their chemical or physical properties6%
G06KGraphical data reading6%
G06TImage data processing or generation, in general6%
B24BMachines, devices, or processes for grinding or polishing3%
C23CCoating metallic material3%
F16LPipes3%
PatentTitleYear
9,734,572'System and method for defect analysis of a substrate'20179,449,656'Memory with bit cell header transistor'20169,412,742'Layout design for manufacturing a memory cell'20168,965,102'System and method for defect analysis of a substrate'20158,665,654'Memory edge cell'20148,482,990'Memory edge cell'20138,226,128'Releasable nut-free C-clip secured pipe fitting'20128,021,955'Method characterizing materials for a trench isolation structure having low trench parasitic capacitance'20117,619,294'Shallow trench isolation structure with low trench parasitic capacitance'20097,001,823'Method of manufacturing a shallow trench isolation structure with low trench parasitic capacitance'20066,989,331'Hard mask removal'20066,916,700'Mixed-mode process'20056,737,342'Composite spacer scheme with low overlapped parasitic capacitance'20046,727,165'Fabrication of metal contacts for deep-submicron technologies'20046,613,637'Composite spacer scheme with low overlapped parasitic capacitance'20036,604,257'Apparatus and method for cleaning a conduit'20036,586,332'Deep submicron silicide blocking'20036,391,768'Process for CMP removal of excess trench or via filler metal which inhibits formation of concave regions on oxide surface of integrated circuit structure'20026,319,836'Planarization system'20016,315,649'Wafer mounting plate for a polishing apparatus and method of using'20016,127,286'Apparatus and process for deposition of thin film on semiconductor substrate while inhibiting particle formation and deposition'20005,851,890'Process for forming integrated circuit structure with metal silicide contacts using notched sidewall spacer on gate electrode'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2011Patents assigned to LSI LOGIC CORP (11)· patent assignee history
1998–2011Based in Fremont, CA, US· patent location history
2001–2015Patents assigned to TAIWAN SEMICONDUCTOR MFG (6)· patent assignee history
2005Based in Taoyuan, TW· patent location history
2012–2013Patents assigned to LEE MING-YI (2)· patent assignee history
2012Based in Taipei, TW· patent location history
2013Patents assigned to CHEN JUNG-HSUAN (1)· patent assignee history
2013–2016Based in Zhudong Township, TW· patent location history
2015–2017Based in Zhu-ki, TW· patent location history
2016–2017Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| LSI LOGIC CORP | 11 | 1998–2011 |
| TAIWAN SEMICONDUCTOR MFG | 6 | 2001–2015 |
| TAIWAN SEMICONDUCTOR MFG CO LTD | 3 | 2016–2017 |
| LEE MING-YIself | 2 | 2012–2013 |
| CHEN JUNG-HSUAN | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Fremont, California, US | 12 | 1998–2011 |
| Zhudong Township, TW | 4 | 2013–2016 |
| Zhu-ki, TW | 2 | 2015–2017 |
| Taipei, TW | 1 | 2012 |
| Taoyuan, TW | 1 | 2005 |