Inventor

Alexander Erik Mericas

Inventor
Austin, TX, US

Overview

46→
Patents
2002–2019
Patent span
Physics
Primary field (CPC G)

Patents· 46 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing92%
G21CNuclear reactors4%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution4%
PatentTitleYear
10,169,187Processor core having a saturating event counter for making performance measurements20199,495,170'Determining each stall reason for each stalled instruction within a group of instructions during a pipeline stall'20169,405,548'Prioritizing instructions based on the number of delay cycles'20169,280,438'Autonomic hotspot profiling using paired performance sampling'20169,229,746'Identifying load-hit-store conflicts'20169,229,745'Identifying load-hit-store conflicts'20168,832,416'Method and apparatus for instruction completion stall identification in an information handling system'20148,635,436'Determining each stall reason for each stalled instruction within a group of instructions during a pipeline stall'20148,615,742'Autonomic hotspot profiling using paired performance sampling'20138,612,730'Hardware assist thread for dynamic performance profiling'20138,514,999'Floating-point event counters with automatic prescaling'20138,479,184'General purpose emit for use in value profiling'20138,234,484'Quantifying completion stalls using instruction sampling'20128,055,809'System and method for distributing signal with efficiency over microprocessor'20117,992,051'Method, apparatus, and computer program product in a processor for dynamically during runtime allocating memory for in-memory hardware tracing'20117,913,123'Concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers'20117,844,860'Apparatus and computer program product in a processor for performing in-memory tracing using existing communication paths'20107,711,994'Apparatus, system and computer program product for seamlessly integrating thermal event information data with performance monitor data'20107,620,801'Methods to randomly or pseudo-randomly, without bias, select instruction for performance analysis in a microprocessor'20097,617,385'Method and apparatus for measuring pipeline stalls in a microprocessor'20097,500,138'Simplified event selection for a performance monitor unit'20097,472,315'Method of seamlessly integrating thermal event information data with performance monitor data'20087,437,618'Method in a processor for dynamically during runtime allocating memory for in-memory hardware tracing'20087,437,617'Method, apparatus, and computer program product in a processor for concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers'20087,421,619'Method in a processor for performing in-memory tracing using existing communication paths'20087,225,110'Extending width of performance monitor counters'20077,225,105'Extending width of performance monitor counters'20077,194,608'Method, apparatus and computer program product for identifying sources of performance events'20077,086,035'Method and system for counting non-speculative events in a speculative processor'20067,051,177'Method for measuring memory latency in a hierarchical memory system'20067,047,398'Analyzing instruction completion delays in a processor'20066,970,999'Counting latencies of an instruction table flush, refill and instruction execution using a plurality of assigned counters'20056,910,120'Speculative counting of performance events with rewind counter'20056,895,399'Method, system, and computer program product for dynamically allocating resources'20056,804,770'Method and apparatus for using past history to avoid flush conditions in a microprocessor'20046,748,522'Performance monitoring based on instruction sampling in a microprocessor'20046,718,403'Hierarchical selection of direct and indirect counting events in a performance monitor unit'20046,694,427'Method system and apparatus for instruction tracing with out of order processors'20046,629,170'Method and apparatus for a byte lane selectable performance monitor bus'20036,574,727'Method and apparatus for instruction sampling for performance monitoring and debug'20036,550,002'Method and system for detecting a flush of an instruction without a flush indicator'20036,539,500'System and method for tracing'20036,539,502'Method and apparatus for identifying instructions for performance monitoring in a microprocessor'20036,530,042'Method and apparatus for monitoring the performance of internal queues in a microprocessor'20036,446,029'Method and system for providing temporal threshold support during performance monitoring of a pipelined processor'20026,415,378'Method and system for tracking the progress of an instruction in an out-of-order processor'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2019Patents assigned to IBM (46)· patent assignee history
2002–2019Based in Austin, TX, US· patent location history
2012–2019Patents assigned to INDUKURU VENKAT RAJEEV (6)· patent assignee history
2012–2019Patents assigned to MERICAS ALEXANDER ERIK (6)· patent assignee history
2013–2016Patents assigned to INDUKURU VENKAT R (4)· patent assignee history
2013–2016Patents assigned to MERICAS ALEXANDER E (4)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM462002–2019
INDUKURU VENKAT RAJEEV62012–2019
MERICAS ALEXANDER ERIKself62012–2019
INDUKURU VENKAT R42013–2016
MERICAS ALEXANDER Eself42013–2016
Locations
LocationPatentsSpan
Austin, Texas, US462002–2019