Inventor

David Shippy

Inventor

Austin, TX, US

Overview

51→

Patents

1990–2018

Patent span

Physics

Primary field (CPC G)

Patents· 51 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing88%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use10%

Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications2%

PatentTitleYear

10,095,647Accelerator architecture on a programmable platform2018 9,329,666'Power throttling queue'2016 9,164,570'Dynamic re-configuration for low power in a data processor'2015 8,082,423'Generating a flush vector from a first execution unit directly to every other execution unit of a plurality of execution units in order to block all register updates'2011 8,051,315'Power throttling apparatus'2011 7,953,960'Method and apparatus for delaying a load miss flush until issuing the dependent instruction'2011 7,913,070'Time-of-life counter for handling instruction flushes from a queue'2011 7,900,024'Handling data cache misses out-of-order for asynchronous pipelines'2011 7,831,808'Queue design system supporting dependency checking and issue for SIMD instructions within a general purpose processor'2010 7,769,985'Load address dependency mechanism system and method in a high frequency, low power processor system'2010 7,681,056'Dynamic power management in a processor design'2010 7,596,682'Architected register file system utilizes status and control registers to control read/write operations between threads'2009 7,496,776'Power throttling method and apparatus'2009 7,490,224'Time-of-life counter design for handling instruction flushes from a queue'2009 7,484,052'Distributed address arbitration scheme for symmetrical multiprocessor system'2009 7,461,239'Apparatus and method for handling data cache misses out-of-order for asynchronous pipelines'2008 7,401,242'Dynamic power management in a processor design'2008 7,370,176'System and method for high frequency stall design'2008 7,363,468'Load address dependency mechanism system and method in a high frequency, low power processor system'2008 7,350,056'Method and apparatus for issuing instructions from an issue queue in an information handling system'2008 7,328,330'Queue design supporting dependency checking and issue for SIMD instructions within a general purpose processor'2008 7,313,673'Fine grained multi-thread dispatch block mechanism'2007 7,120,748'Software-controlled cache set management'2006 7,114,035'Software-controlled cache set management with software-generated class identifiers'2006 7,103,748'Memory management for real-time applications'2006 7,093,080'Method and apparatus for coherent memory structure of heterogeneous processor systems'2006 7,062,612'Updating remote locked cache'2006 6,981,072'Memory management in multiprocessor system'2005 6,961,820'System and method for identifying and accessing streaming data in a locked portion of a cache'2005 6,957,305'Data streaming mechanism in a microprocessor'2005 6,820,143'On-chip data transfer in multi-processor system'2004 6,658,555'Determining successful completion of an instruction by comparing the number of pending instruction cycles with a number based on the number of stages in the pipeline'2003 6,654,876'System for rejecting and reissuing instructions after a variable delay time period'2003 6,543,002'Recovery from hang condition in a microprocessor'2003 6,490,653'Method and system for optimally issuing dependent instructions based on speculative L2 cache hit in a data processing system'2002 6,349,382'System for store forwarding assigning load and store instructions to groups and reorder queues to keep track of program order'2002 6,336,168'System and method for merging multiple outstanding load miss instructions'2002 6,336,183'System and method for executing store instructions'2002 6,298,436'Method and system for performing atomic memory accesses in a processor system'2001 6,289,428'Superscaler processor and method for efficiently recovering from misaligned data addresses'2001 6,237,081'Queuing method and apparatus for facilitating the rejection of sequential instructions in a processor'2001 6,226,722'Integrated level two cache and controller with multiple ports, L1 bypass and concurrent accessing'2001 6,061,780'Execution unit chaining for single cycle extract instruction having one serial shift left and one serial shift right execution units'2000 6,003,125'High performance adder for multiple parallel add operations'1999 5,822,755'Dual usage memory selectively behaving as a victim cache for L1 cache or as a tag array for L2 cache'1998 5,822,758'Method and system for high performance dynamic and user programmable cache arbitration'1998 5,210,828'Multiprocessing system with interprocessor communications facility'1993 4,974,147'Programmable quiesce apparatus for retry, recovery and debug'1990 4,961,140'Apparatus and method for extending a parallel synchronous data and message bus'1990 4,953,081'Least recently used arbiter with programmable high priority mode and performance monitor'1990 4,943,984'Data processing system parallel data bus having a single oscillator clocking apparatus'1990

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1990–2011Patents assigned to IBM (46)· patent assignee history

1990Based in Endwell, NY, US· patent location history

1993–2018Based in Austin, TX, US· patent location history

1998Based in Houston, TX, US· patent location history

1999–2000Patents assigned to TEXAS INSTRUMENTS INC (2)· patent assignee history

1999–2000Based in Bellaire, TX, US· patent location history

2008Based in Georgetown, TX, US· patent location history

2011Patents assigned to ABERNATHY CHRISTOPHER MICHAEL (1)· patent assignee history

2015–2016Patents assigned to ADVANCED MICRO DEVICES INC (2)· patent assignee history

2018Patents assigned to ALTERA CORP (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	46	1990–2011
ADVANCED MICRO DEVICES INC	2	2015–2016
TEXAS INSTRUMENTS INC	2	1999–2000
ABERNATHY CHRISTOPHER MICHAEL	1	2011
ALTERA CORP	1	2018

Locations

Location	Patents	Span
Austin, Texas, US	42	1993–2018
Endwell, New York, US	4	1990
Bellaire, Texas, US	2	1999–2000
Houston, Texas, US	2	1998
Georgetown, Texas, US	1	2008