Inventor

Fumio Horiguchi

Inventor
Tokyo, JP

Overview

33→
Patents
1985–2006
Patent span
Electricity
Primary field (CPC H)

Patents· 33 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Bprimary
H10BElectronic memory devices39%
H10DInorganic electric semiconductor devices20%
G11CStatic stores13%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests9%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
H03FAmplifiers3%
H03KPulse technique3%
B82YSpecific uses or applications of nanostructures1%
PatentTitleYear
7,075,820'Semiconductor memory device for dynamically storing data with channel body of transistor used as storage node'20067,042,040'Semiconductor device and method for manufacturing the same'20067,042,753'Multi-value magnetic random access memory with stacked tunnel magnetoresistance (TMR) elements'20066,891,225'Dynamic semiconductor memory device'20056,548,848'Semiconductor memory device'20036,292,390'Semiconductor device'20016,232,822'Semiconductor device including a bipolar transistor biased to produce a negative base current by the impact ionization mechanism'20015,895,946'MOS random access memory having array of trench type one-capacitor/one-transistor memory cells'19995,731,609'MOS random access memory having array of trench type one-capacitor/one-transistor memory cells'19985,561,311'Semiconductor memory with insulation film embedded in groove formed on substrate'19965,488,242'Semiconductor memory device'19965,477,071'MOS random access memory having array of trench type one-capacitor/one-transistor memory cells'19955,387,532'Semiconductor memory having capacitor electrode formed above bit line'19955,371,024'Semiconductor device and process for manufacturing the same'19945,363,325'Dynamic semiconductor memory device having high integration density'19945,350,708'Method of making dynamic random access semiconductor memory device'19945,258,635'MOS-type semiconductor integrated circuit device'19935,250,830'Dynamic type semiconductor memory device and its manufacturing method'19935,235,199'Semiconductor memory with pad electrode and bit line under stacked capacitor'19935,227,319'Method of manufacturing a semiconductor device'19935,202,751'Semiconductor integrated circuit'19935,138,412'Dynamic ram, having an improved large capacitance'19925,106,774'Method of making trench type dynamic random access memory device'19925,049,957'MOS type dynamic random access memory'19915,043,298'Process for manufacturing a DRAM cell'19914,992,389'Making a self aligned semiconductor device'19914,979,014'MOS transistor'19904,831,433'Semiconductor device'19894,800,530'Semiconductor memory system with dynamic random access memory cells'19894,799,193'Semiconductor memory devices'19894,641,280'High-density semiconductor memory device with charge-coupling memory cells'19874,628,488'Semiconductor memory device with a refresh mechanism'19864,505,025'Method for manufacturing a semiconductor device'1985

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1985–1986Patents assigned to TOKYO SHIBAURA ELECTRIC CO (2)· patent assignee history
1985–2006Based in Tokyo, JP· patent location history
1986Based in Itabashi-ku, JP· patent location history
1987–2006Patents assigned to TOSHIBA KK (30)· patent assignee history
1989Patents assigned to KABUSHIKI KASIHA TOSHIBA (1)· patent assignee history
1989–1992Based in Kawasaki, JP· patent location history
2006Based in Minato-ku, JP· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TOSHIBA KK301987–2006
TOKYO SHIBAURA ELECTRIC CO21985–1986
KABUSHIKI KASIHA TOSHIBA11989
Locations
LocationPatentsSpan
Tokyo, JP271985–2006
Kawasaki, JP41989–1992
Minato-ku, JP12006
Itabashi-ku, JP11986