Inventor
Hing Y. To
Inventor
Folsom, CA, US
Overview
Patents· 27 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing40%
G11CStatic stores22%
H03KPulse technique9%
H04LTransmission of digital information, e.g. telegraphic communication9%
H05KPrinted circuits9%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use4%
G01RMeasuring electric variables2%
H03FAmplifiers2%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses2%
PatentTitleYear
10,860,776Printed circuit board (PCB) modular design20207,954,001'Nibble de-skew method, apparatus, and system'20117,805,627'Clock synchronization scheme for deskewing operations in a data interface'20107,692,457'Dual-path clocking architecture'20107,602,859'Calibrating integrating receivers for source synchronous protocol'20097,459,938'Method and apparatus for power efficient and scalable memory interface'20087,446,572'Method and system for a configurable Vcc reference and Vss reference differential current mode transmitter'20087,401,246'Nibble de-skew method, apparatus, and system'20087,388,795'Modular memory controller clocking architecture'20087,334,148'Optimization of integrated circuit device I/O bus timing'20087,324,403'Latency normalization by balancing early and late clocks'20087,245,682'Determining an optimal sampling clock'20077,243,176'Method and apparatus for power efficient and scalable memory interface'20077,194,559'Slave I/O driver calibration using error-nulling master reference'20077,117,401'Method and apparatus for optimizing timing for a multi-drop bus'20067,010,637'Single-ended memory interface system'20066,973,603'Method and apparatus for optimizing timing for a multi-drop bus'20056,941,484'Synthesis of a synchronization clock'20056,885,959'Circuit and method for calibrating DRAM pullup Ron to pulldown Ron'20056,771,515'Systems having modules with on die terminations'20046,747,483'Differential memory interface system'20046,725,390'Method and an apparatus for adjusting clock signal to sample data'20046,724,082'Systems having modules with selectable on die terminations'20046,631,083'Systems with modules and clocking therefore'20036,597,202'Systems with skew control between clock and data signals'20036,507,218'Method and apparatus for reducing back-to-back voltage glitch on high speed data bus'20036,051,999'Low voltage programmable complementary input stage sense amplifier'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2011Patents assigned to INTEL CORP (26)· patent assignee history
2000–2008Based in Folsom, CA, US· patent location history
2005–2020Based in Cupertino, CA, US· patent location history
2020Patents assigned to XILINX INC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 26 | 2000–2011 |
| XILINX INC | 1 | 2020 |
Locations
| Location | Patents | Span |
|---|---|---|
| Folsom, California, US | 16 | 2000–2008 |
| Cupertino, California, US | 11 | 2005–2020 |