Inventor

Andy L. Lee

Inventor

San Jose, CA, US

Overview

1999–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 173 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Kprimary

H03KPulse technique48%

G11CStatic stores21%

G06FElectric digital data processing13%

G01RMeasuring electric variables3%

H01LSemiconductor devices3%

H10DInorganic electric semiconductor devices3%

H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses2%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h102%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%

H10BElectronic memory devices1%

PatentTitleYear

10,573,375Methods and circuitry for programming non-volatile resistive switches using varistors2020 10,541,205Manufacture of interconnects for integration of multiple integrated circuits2020 10,447,275Integrated circuits with programmable non-volatile resistive switch elements2019 10,269,426Integrated circuits with complementary non-volatile resistive memory elements2019 10,177,766Omnibus logic element2019 10,121,534Integrated circuit with overdriven and underdriven pass gates2018 10,090,840Integrated circuits with programmable non-volatile resistive switch elements2018 10,043,716N-well/P-well strap structures2018 9,984,734Programmable integrated circuits with in-operation reconfiguration capability2018 9,755,647'Techniques for handling high voltage circuitry in an integrated circuit'2017 9,667,314'Programmable repeater circuits and methods'2017 9,658,830'Structures for LUT-based arithmetic in PLDs'2017 9,654,109'Hardened programmable devices'2017 9,607,671'Programmable integrated circuits with in-operation reconfiguration capability'2017 9,548,103'Scaleable look-up table based memory'2017 9,501,407'First-in-first-out memory with dual memory banks'2016 9,496,875'Omnibus logic element'2016 9,496,268'Integrated circuits with asymmetric and stacked transistors'2016 9,449,962'N-well/P-well strap structures'2016 9,412,436'Memory elements with soft error upset immunity'2016 9,397,095'Power and die size optimization in FinFETs'2016 9,299,396'Programmable integrated circuits with in-operation reconfiguration capability'2016 9,224,438'Multiple data rate memory interface architecture'2015 9,165,931'Apparatus for field-programmable gate array with configurable architecture and associated methods'2015 9,123,437'Scaleable look-up table based memory'2015 9,099,531'Metal routing in advanced process technologies'2015 9,094,014'PLD architecture for flexible placement of IP function blocks'2015 8,995,175'Memory circuit with PMOS access transistors'2015 8,878,567'Omnibus logic element'2014 8,797,790'Memory elements with soft error upset immunity'2014 8,788,550'Structures for LUT-based arithmetic in PLDs'2014 8,750,026'Integrated circuits with asymmetric and stacked transistors'2014 8,732,635'Apparatus and methods for power management in integrated circuits'2014 8,732,646'PLD architecture for flexible placement of IP function blocks'2014 8,716,809'Hardened programmable devices'2014 8,711,614'Memory elements with increased write margin and soft error upset immunity'2014 8,698,516'Apparatus for improving performance of field programmable gate arrays and associated methods'2014 8,644,100'Scaleable look-up table based memory'2014 8,593,174'Omnibus logic element for packing or fracturing'2013 8,593,195'High performance memory interface circuit architecture'2013 8,514,994'Double data rate operation in an integrated circuit'2013 8,514,001'Memory interface phase-shift circuitry to support multiple frequency ranges'2013 8,502,558'Computer-aided design tools and memory element power supply circuitry for selectively overdriving circuit blocks'2013 8,487,651'Multiple data rate memory interface architecture'2013 8,482,963'Integrated circuits with asymmetric and stacked transistors'2013 8,461,869'Apparatus for configuring performance of field programmable gate arrays and associated methods'2013 8,407,649'PLD architecture for flexible placement of IP function blocks'2013 8,369,175'Memory elements with voltage overstress protection'2013 8,305,121'High-performance memory interface circuit architecture'2012 8,289,755'Volatile memory elements with soft error upset immunity'2012 8,248,110'Clock switch-over circuits and methods'2012 8,237,465'Omnibus logic element for packing or fracturing'2012 8,217,678'Fracturable lookup table and logic element'2012 8,217,464'N-well/P-well strap structures'2012 8,201,129'PLD architecture for flexible placement of IP function blocks'2012 8,198,914'Apparatus and methods for adjusting performance of programmable logic devices'2012 8,188,781'Memory interface phase-shift circuitry to support multiple frequency ranges'2012 8,130,574'Error detection on programmable logic resources'2012 8,105,885'Hardened programmable devices'2012 8,103,975'Apparatus and methods for optimizing the performance of programmable logic devices using multiple supply voltage'2012 8,081,502'Memory elements with body bias control'2011 8,072,237'Computer-aided design tools and memory element power supply circuitry for selectively overdriving circuit blocks'2011 8,064,280'Scaleable look-up table based memory'2011 8,030,962'Configuration random access memory'2011 7,994,816'Multiple data rate memory interface architecture'2011 7,969,215'High-performance memory interface circuit architecture'2011 7,948,792'Memory and techniques for using same'2011 7,936,184'Apparatus and methods for adjusting performance of programmable logic devices'2011 7,920,410'Memory elements with increased write margin and soft error upset immunity'2011 7,911,240'Clock switch-over circuits and methods'2011 7,911,230'Omnibus logic element for packing or fracturing'2011 7,907,460'Error detection on programmable logic resources'2011 7,839,165'User-accessible freeze-logic for dynamic power reduction and associated methods'2010 7,812,633'Apparatus and method for the arithmetic over-ride of look up table outputs in a programmable logic device'2010 7,800,405'Passgate structures for use in low-voltage applications'2010 7,800,401'Fracturable lookup table and logic element'2010 7,800,400'Configuration random access memory'2010 7,768,430'Look-up table based memory'2010 7,737,751'Periphery clock distribution network for a programmable logic device'2010 7,705,628'Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers'2010 7,702,978'Soft error location and sensitivity detection for programmable devices'2010 7,671,625'Omnibus logic element'2010 7,671,626'Versatile logic element and logic array block'2010 7,656,191'Distributed memory in field-programmable gate array integrated circuit devices'2010 7,605,603'User-accessible freeze-logic for dynamic power reduction and associated methods'2009 7,584,447'PLD architecture for flexible placement of IP function blocks'2009 7,577,055'Error detection on programmable logic resources'2009 7,571,413'Testing circuitry for programmable logic devices with selectable power supply voltages'2009 7,558,812'Structures for LUT-based arithmetic in PLDs'2009 7,557,608'Passgate structures for use in low-voltage applications'2009 7,538,579'Omnibus logic element'2009 7,535,275'High-performance memory interface circuit architecture'2009 7,512,849'Reconfigurable programmable logic system with configuration recovery mode'2009 7,504,855'Multiple data rate memory interface architecture'2009 7,460,431'Implementation of double data rate embedded memory in programmable devices'2008 7,432,734'Versatile logic element and logic array block'2008 7,405,589'Apparatus and methods for power management in integrated circuits'2008 7,400,167'Apparatus and methods for optimizing the performance of programmable logic devices'2008 7,391,236'Distributed memory in field-programmable gate array integrated circuit devices'2008 7,346,861'Programmable logic devices with two-phase latch circuitry'2008 7,323,903'Soft core control of dedicated memory interface hardware in a programmable logic device'2008 7,323,902'Fracturable lookup table and logic element'2008 7,312,632'Fracturable lookup table and logic element'2007 7,310,757'Error detection on programmable logic resources'2007 7,287,189'I/O configuration and reconfiguration trigger through testing interface'2007 7,236,008'Multiple size memories in a programmable logic device'2007 7,227,395'High-performance memory interface circuit architecture'2007 7,218,133'Versatile logic element and logic array block'2007 7,215,140'Programmable logic device having regions of non-repairable circuitry within an array of repairable circuitry and associated configuration hardware and method'2007 7,205,791'Bypass-able carry chain in a programmable logic device'2007 7,196,542'Techniques for providing increased flexibility to input/output banks with respect to supply voltages'2007 7,176,714'Multiple data rate memory interface architecture'2007 7,167,022'Omnibus logic element including look up table based logic elements'2007 7,138,844'Variable delay circuitry'2006 7,126,399'Memory interface phase-shift circuitry to support multiple frequency ranges'2006 7,123,051'Soft core control of dedicated memory interface hardware in a programmable logic device'2006 7,119,574'Passage structures for use in low-voltage applications'2006 7,112,992'Configuration shift register'2006 7,103,813'Method and apparatus for testing interconnect bridging faults in an FPGA'2006 7,064,577'Method and apparatus for supporting variable speed configuration hardware'2006 7,061,268'Initializing a carry chain in a programmable logic device'2006 7,058,920'Methods for designing PLD architectures for flexible placement of IP function blocks'2006 7,010,777'Shared lookup table enhancements for the efficient implementation of barrel shifters'2006 7,000,161'Reconfigurable programmable logic system with configuration recovery mode'2006 6,970,014'Routing architecture for a programmable logic device'2005 6,965,249'Programmable logic device with redundant circuitry'2005 6,943,580'Fracturable lookup table and logic element'2005 6,937,064'Versatile logic element and logic array block'2005 6,897,678'Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits'2005 6,895,570'System and method for optimizing routing lines in a programmable logic device'2005 6,879,183'Programmable logic device architectures with super-regions having logic regions and a memory region'2005 6,859,065'Use of dangling partial lines for interfacing in a PLD'2005 6,857,043'Shift register implementations of first-in/first-out memories utilizing a double increment gray code counter'2005 6,842,040'Differential interconnection circuits in programmable logic devices'2005 6,842,039'Configuration shift register'2005 6,826,741'Flexible I/O routing resources'2004 6,798,242'Programmable logic device with hierarchical interconnection resources'2004 6,661,253'Passgate structures for use in low-voltage applications'2003 6,653,862'Use of dangling partial lines for interfacing in a PLD'2003 6,630,842'Routing architecture for a programmable logic device'2003 6,605,962'PLD architecture for flexible placement of IP function blocks'2003 6,577,160'Programmable logic device with hierarchical interconnection resources'2003 6,563,367'Interconnection switch structures'2003 6,515,508'Differential interconnection circuits in programmable logic devices'2003 6,481,000'Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits'2002 6,480,028'Programmable logic device architectures with super-regions having logic regions and memory region'2002 6,462,597'Trip-point adjustment and delay chain circuits'2002 6,462,577'Configurable memory structures in a programmable logic device'2002 6,417,694'Programmable logic device with hierarchical interconnection resources'2002 6,411,124'Programmable logic device logic modules with shift register capabilities'2002 6,384,625'Programmable logic devices with enhanced multiplexing capabilities'2002 6,353,551'Static random access memory circuits'2002 6,344,755'Programmable logic device with redundant circuitry'2002 6,335,634'Circuitry and methods for internal interconnection of programmable logic devices'2002 6,300,794'Programmable logic device with hierarchical interconnection resources'2001 6,278,288'Programmable logic device with enhanced multiplexing capabilities in interconnect resources'2001 6,255,846'Programmable logic devices with enhanced multiplexing capabilities'2001 6,225,823'Input/output circuitry for programmable logic devices'2001 6,215,326'Programmable logic device architecture with super-regions having logic regions and a memory region'2001 6,202,185'Methods and apparatus for facilitating scan testing of circuitry'2001 6,201,404'Programmable logic device with redundant circuitry'2001 6,181,160'Programmable logic device with hierarchical interconnection resources'2001 6,166,559'Redundancy circuitry for logic circuits'2000 6,157,210'Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits'2000 6,128,215'Static random access memory circuits'2000 6,121,790'Programmable logic device with enhanced multiplexing capabilities in interconnect resources'2000 6,107,825'Input/output circuitry for programmable logic devices'2000 6,107,824'Circuitry and methods for internal interconnection of programmable logic devices'2000 6,091,258'Redundancy circuitry for logic circuits'2000 6,084,427'Programmable logic devices with enhanced multiplexing capabilities'2000 6,034,536'Redundancy circuitry for logic circuits'2000 6,028,809'Programmable logic device incorporating a tristateable logic array block'2000 5,977,793'Programmable logic device with hierarchical interconnection resources'1999

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1999–2019Patents assigned to ALTERA CORP (167)· patent assignee history

1999–2020Based in San Jose, CA, US· patent location history

2011–2016Patents assigned to LEE ANDY L (33)· patent assignee history

2011–2015Patents assigned to RAHIM IRFAN (11)· patent assignee history

2012–2016Patents assigned to LEWIS DAVID (11)· patent assignee history

2012–2014Patents assigned to WATT JEFFREY T (7)· patent assignee history

2018–2020Based in Sunnyvale, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
ALTERA CORP	167	1999–2019
LEE ANDY Lself	33	2011–2016
LEWIS DAVID	11	2012–2016
RAHIM IRFAN	11	2011–2015
WATT JEFFREY T	7	2012–2014

Locations

Location	Patents	Span
San Jose, California, US	167	1999–2020
Sunnyvale, California, US	6	2018–2020