Inventor
Chih-Hsuan CHEN
Inventor
TW
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices27%
H01LSemiconductor devices23%
B82YSpecific uses or applications of nanostructures14%
H10BElectronic memory devices14%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
G11CStatic stores2%
G06FElectric digital data processing1%
H03KPulse technique1%
PatentTitleYear
12,563,825Integrated circuit structure with a reduced amount of defects and methods for fabricating the same202612,477,811High-k gate dielectric202512,356,660Multi-gate device and related methods202512,336,281Gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof202512,315,738Method of forming a gate structure including semiconductor material implantation into dummy gate stack202512,294,030Nano-sheet-based complementary metal-oxide-semiconductor devices with asymmetric inner spacers202512,250,803Device and method for tuning threshold voltage202512,249,636Tuning gate lengths in multi-gate field effect transistors202512,219,747Memory active region layout for improving memory performance202512,218,227Semiconductor structure202512,159,924Structure and method for multigate devices with suppressed diffusion202412,040,325Integrated circuit structure with a reduced amount of defects and methods for fabricating the same202412,027,425Method of forming a gate structure202411,996,484Nano-sheet-based complementary metal-oxide-semiconductor devices with asymmetric inner spacers202411,949,016Multi-gate device and related methods202411,908,510Fuse device and operation method thereof202411,908,866Gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof202411,862,706High-K gate dielectric202411,742,416Semiconductor structure and method for manufacturing the same202311,482,610Method of forming a gate structure202211,349,009High-k gate dielectric202211,329,042Gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof202211,239,121Metal gate contacts and methods of forming the same2022Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2022–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (22)· patent assignee history
2022Patents assigned to TAIWAN SEMICONDUCTOR MFG (1)· patent assignee history
2022–2026Based in TW· patent location history
2024Patents assigned to NANYA TECHNOLOGY CORP (1)· patent assignee history
2025Patents assigned to TAIWAN SEMICONDUCTOR MANUFACTORING COMPANY LTD (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 22 | 2022–2026 |
| NANYA TECHNOLOGY CORP | 1 | 2024 |
| TAIWAN SEMICONDUCTOR MANUFACTORING COMPANY LTD | 1 | 2025 |
| TAIWAN SEMICONDUCTOR MFG | 1 | 2022 |
Locations
| Location | Patents | Span |
|---|---|---|
| TW | 23 | 2022–2026 |