Inventor

Robert M. Nickerson

Inventor

Chandler, AZ, US

Overview

27→

Patents

2004–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 27 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1039%

H01LSemiconductor devices22%

H05KPrinted circuits14%

Y10TTechnical subjects covered by former us classification12%

C09JAdhesives4%

B23KSoldering or unsoldering1%

B29CShaping or joining of plastics1%

B29KIndexing scheme associated with subclasses b29b, b29c or b29d, relating to moulding materials or to materials for moulds, reinforcements, fillers or preformed parts, e.g. inserts1%

B29LIndexing scheme associated with subclass b29c, relating to particular articles1%

G11CStatic stores1%

PatentTitleYear

11,056,466Package on package thermal transfer systems and methods2021 10,607,976Offset interposers for large-bottom packages and large-die package-on-package structures2020 10,446,530Offset interposers for large-bottom packages and large-die package-on-package structures2019 10,438,930Package on package thermal transfer systems and methods2019 10,231,338Methods of forming trenches in packages structures and structures formed thereby2019 10,128,225Interconnect structures with polymer core2018 10,121,722Architecture material and process to improve thermal performance of the embedded die package2018 9,691,728'BBUL top side substrate layer enabling dual sided silicon interconnect and stacking flexibility'2017 9,691,727'Pad-less interconnect for electrical coreless substrate'2017 9,666,549'Methods for solder for through-mold interconnect'2017 9,613,934'Interconnect structures with polymer core'2017 9,177,911'Package substrates with multiple dice'2015 9,159,690'Tall solders for through-mold interconnect'2015 9,049,807'Processes of making pad-less interconnect for electrical coreless substrate'2015 8,987,918'Interconnect structures with polymer core'2015 8,742,597'Package substrates with multiple dice'2014 8,674,519'Microelectronic package and method of manufacturing same'2014 8,513,792'Package-on-package interconnect stiffener'2013 7,818,878'Integrated circuit device mounting with folded substrate and interposer'2010 7,375,978'Method and apparatus for trace shielding and routing on a substrate'2008 7,358,444'Folded substrate with interposer package for integrated circuit devices'2008 7,304,373'Power distribution within a folded flex package method and apparatus'2007 7,302,756'Bond finger on via substrate, process of making same, package made thereby, and method of assembling same'2007 7,250,684'Circular wire-bond pad, package made therewith, and method of assembling same'2007 7,205,649'Ball grid array copper balancing'2007 7,190,068'Bottom heat spreader'2007 6,794,760'Integrated circuit interconnect'2004

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2004–2021Patents assigned to INTEL CORP (27)· patent assignee history

2004–2021Based in Chandler, AZ, US· patent location history

2013–2019Patents assigned to NICKERSON ROBERT M (3)· patent assignee history

2013–2014Patents assigned to ARANA LEONEL R (2)· patent assignee history

2013Patents assigned to GANESAN SANKA (1)· patent assignee history

2014–2015Patents assigned to NICKERSON ROBERT (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	27	2004–2021
NICKERSON ROBERT Mself	3	2013–2019
ARANA LEONEL R	2	2013–2014
NICKERSON ROBERTself	2	2014–2015
GANESAN SANKA	1	2013

Locations

Location	Patents	Span
Chandler, AZ, US	27	2004–2021