Inventor
Perry H. Wang
Inventor
San Jose, CA, US
Overview
Patents· 43 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing93%
G06NComputing arrangements based on specific computational models2%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications2%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%
PatentTitleYear
10,877,910Programmable event driven yield mechanism which may activate other threads202010,635,438Method and system to provide user-level multithreading202010,628,153Method and system to provide user-level multithreading202010,613,858Method and system to provide user-level multithreading202010,585,667Method and system to provide user-level multithreading202010,534,613Supporting learned branch predictors202010,459,858Programmable event driven yield mechanism which may activate other threads201910,324,872Interrupt-vector translation lookaside buffer20199,952,859Method and system to provide user-level multithreading20189,910,796'Programmable event driven yield mechanism which may activate other threads'20189,785,576'Hardware-assisted virtualization for implementing secure video output path'20179,442,721'Method and system to provide user-level multithreading'20169,189,230'Method and system to provide concurrent user-level, non-privileged shared resource thread creation and execution'20158,868,887'Programmable event driven yield mechanism which may activate other threads'20148,843,728'Processor for enabling inter-sequencer communication following lock competition and accelerator registration'20148,719,806'Speculative multi-threading for instruction prefetch and/or trace pre-build'20148,612,949'Methods and apparatuses for compiler-creating helper threads for multi-threading'20138,522,220'Post-pass binary adaptation for software-based speculative precomputation'20138,380,963'Apparatus and method for enabling inter-sequencer communication following lock competition and accelerator registration'20138,296,743'Compiler and runtime for heterogeneous multiprocessor systems'20128,095,920'Post-pass binary adaptation for software-based speculative precomputation'20128,078,831'Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors'20118,074,274'User-level privilege management'20118,037,465'Thread-data affinity optimization using compiler'20117,941,791'Programming environment for heterogeneous processor resource integration'20117,904,696'Communication paths for enabling inter-sequencer communication following lock competition and accelerator registration'20117,844,801'Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors'20107,818,547'Method and apparatus for efficient resource utilization for prescient instruction prefetch'20107,814,469'Speculative multi-threading for instruction prefetch and/or trace pre-build'20107,768,518'Enabling multiple instruction stream/multiple data stream extensions on microprocessors'20107,657,880'Safe store for speculative helper threads'20107,631,307'User-programmable low-overhead multithreading'20097,603,546'System, method and apparatus for dependency chain processing'20097,587,584'Mechanism to exploit synchronization overhead to improve multithreaded performance'20097,487,502'Programmable event driven yield mechanism which may activate other threads'20097,404,067'Method and apparatus for efficient utilization for prescient instruction prefetch'20087,398,521'Methods and apparatuses for thread management of multi-threading'20087,328,433'Methods and apparatus for reducing memory latency in a software application'20087,260,705'Apparatus to implement mesocode'20077,228,528'Building inter-block streams from a dynamic execution trace for a program'20077,069,545'Quantization and compression for computation reuse'20066,928,645'Software-based speculative pre-computation and multithreading'20056,883,089'Method and apparatus for processing a predicated instruction using limited predicate slip'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2020Patents assigned to INTEL CORP (41)· patent assignee history
2005–2020Based in San Jose, CA, US· patent location history
2011–2015Patents assigned to WANG HONG (11)· patent assignee history
2011–2015Patents assigned to SHEN JOHN P (6)· patent assignee history
2011–2014Patents assigned to WANG PERRY (6)· patent assignee history
2011–2015Patents assigned to WANG PERRY H (5)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 41 | 2005–2020 |
| WANG HONG | 11 | 2011–2015 |
| SHEN JOHN P | 6 | 2011–2015 |
| WANG PERRYself | 6 | 2011–2014 |
| WANG PERRY Hself | 5 | 2011–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 43 | 2005–2020 |