Inventor
Augustine Wei-Chun Chang
Inventor
Mountain View, CA, US
Overview
Patents· 18 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices16%
H03KPulse technique15%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1015%
H10BElectronic memory devices12%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation10%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution10%
G11CStatic stores7%
H01LSemiconductor devices7%
G06FElectric digital data processing3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
PatentTitleYear
10,666,260Schottky-CMOS asynchronous logic cells202010,373,950Super CMOS devices on a microelectronics system20199,853,643Schottky-CMOS asynchronous logic cells20179,806,072'Super CMOS devices on a microelectronics system'20179,502,379'Super CMOS devices on a microelectronics system'20169,077,340'Super CMOS devices on a microelectronics system'20158,476,689'Super CMOS devices on a microelectronics system'20137,375,548'SCL type FPGA with multi-threshold transistors and method for forming same'20087,135,890'SCL type FPGA with multi-threshold transistors and method for forming same'20067,082,056'Flash memory device and architecture with multi level cells'20066,852,578'Schottky diode static random access memory (DSRAM) device, a method for making same, and CFET based DTL'20056,590,800'Schottky diode static random access memory (DSRAM) device, a method for making same, and CFET based DTL'20036,442,633'Reduced transistors data switch port wherein each of a plurality of transmission gates is coupled to both first and second control signals for selectively enabling'20025,942,777'Memory device including a memory array having a combination of trench capacitor DRAM cells and stacked capacitor DRAM cells'19994,316,319'Method for making a high sheet resistance structure for high density integrated circuits'19824,228,450'Buried high sheet resistance structure for high density integrated circuits with reach through contacts'19804,135,954'Method for fabricating self-aligned semiconductor devices utilizing selectively etchable masking layers'19794,005,469'P-type-epitaxial-base transistor with base-collector Schottky diode clamp'1977Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1977–1982Patents assigned to IBM (4)· patent assignee history
1977–1982Based in Wappingers Falls, NY, US· patent location history
1999–2002Patents assigned to SUN MICROSYSTEMS INC (2)· patent assignee history
1999–2008Based in San Jose, CA, US· patent location history
2005Based in Santa Clara, CA, US· patent location history
2006–2008Patents assigned to SUPER TALENT ELECTRONICS INC (3)· patent assignee history
2013Patents assigned to CHANG AUGUSTINE WEI-CHUN (1)· patent assignee history
2013–2020Based in Mountain View, CA, US· patent location history
2015–2020Patents assigned to SCHOTTKY LSI INC (6)· patent assignee history
2017Based in Mountainview, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SCHOTTKY LSI INC | 6 | 2015–2020 |
| IBM | 4 | 1977–1982 |
| SUPER TALENT ELECTRONICS INC | 3 | 2006–2008 |
| SUN MICROSYSTEMS INC | 2 | 1999–2002 |
| CHANG AUGUSTINE WEI-CHUNself | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Mountain View, California, US | 6 | 2013–2020 |
| San Jose, California, US | 6 | 1999–2008 |
| Wappingers Falls, New York, US | 4 | 1977–1982 |
| Mountainview, California, US | 1 | 2017 |
| Santa Clara, California, US | 1 | 2005 |