Inventor
Andrew F. Glew
Inventor
Hillsboro, OR, US
Overview
Patents· 120 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing82%
H04LTransmission of digital information, e.g. telegraphic communication3%
H04NPictorial communication, e.g. television2%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes1%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications1%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use1%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
F28FDetails of heat-exchange and heat-transfer apparatus, of general application1%
G01SRadio direction-finding1%
G09FDisplaying1%
PatentTitleYear
10,649,773Processors supporting atomic writes to multiword memory locations and methods20209,997,495Non-contacting inductive interconnects20189,813,445'Taint injection and tracking'20179,798,873'Processor operable to ensure code integrity'20179,727,890'Systems and methods for registering advertisement viewing'20179,703,566'Sharing TLB mappings between contexts'20179,575,903'Security perimeter'20179,558,034'Entitlement vector for managing resource allocation'20179,554,487'Microchannel heat transfer with liquid metals'20179,471,373'Entitlement vector for library usage in managing resource allocation and scheduling based on usage and priority'20169,465,657'Entitlement vector for library usage in managing resource allocation and scheduling based on usage and priority'20169,460,290'Conditional security response using taint vector monitoring'20169,443,085'Intrusion detection using taint accumulation'20169,298,918'Taint injection and tracking'20169,176,741'Method and apparatus for segmented sequential storage'20159,170,843'Data handling apparatus adapted for scheduling operations according to resource allocation based on entitlement'20159,098,608'Processor configured to allocate resources using an entitlement vector'20158,955,111'Instruction set adapted for security risk monitoring'20158,947,515'Systems and methods for registering advertisement viewing'20158,943,313'Fine-grained security in federated data sets'20158,930,714'Encrypted memory'20158,904,045'Opportunistic improvement of MMIO request handling based on target reporting of space requirements'20148,813,085'Scheduling threads based on priority utilizing entitlement vectors, weight and usage level'20148,635,415'Managing and implementing metadata in central processing unit using register extensions'20148,296,550'Hierarchical register file with operand capture ports'20128,275,976'Hierarchical instruction scheduler facilitating instruction replay'20128,266,412'Hierarchical store buffer having segmented partitions'20128,055,805'Opportunistic improvement of MMIO request handling based on target reporting of space requirements'20118,037,288'Hybrid branch predictor having negative ovedrride signals'20118,028,152'Hierarchical multi-threading processor for executing virtual threads in a time-multiplexed fashion'20117,996,656'Attaching and virtualizing reconfigurable logic units to a processor'20117,644,258'Hybrid branch predictor using component predictors each having confidence and override signals'20107,318,141'Methods and systems to control virtual machines'20087,308,576'Authenticated code module'20077,149,882'Processor with instructions that operate on different data types stored in the same single logical register file'20066,792,523'Processor with instructions that operate on different data types stored in the same single logical register file'20046,678,816'Method for optimized representation of page table entries'20046,647,482'Method for optimized representation of page table entries'20036,378,062'Method and apparatus for performing a store operation'20026,297,843'System providing video compression/encoding for communications across a network'20016,170,997'Method for executing instructions that operate on different data types stored in the same single logical register file'20016,079,014'Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state'20006,047,369'Flag renaming and flag masks within register alias table'20006,035,393'Stalling predicted prefetch to memory location identified as uncacheable using dummy stall instruction until branch speculation resolution'20005,987,600'Exception handling in a processor that performs speculative out-of-order instruction execution'19995,978,737'Method and apparatus for hazard detection and distraction avoidance for a vehicle'19995,974,523'Mechanism for efficiently overlapping multiple operand types in a microprocessor'19995,956,753'Method and apparatus for handling speculative memory access operations'19995,951,670'Segment register renaming in an out of order processor'19995,948,097'Method and apparatus for changing privilege levels in a computer system without use of a call gate'19995,935,240'Computer implemented method for transferring packed data between register files and memory'19995,913,050'Method and apparatus for providing address-size backward compatibility in a processor using segmented memory'19995,909,696'Method and apparatus for caching system management mode information with other information'19995,881,262'Method and apparatus for blocking execution of and storing load operations during their execution'19995,881,223'Centralized performance monitoring architecture'19995,860,154'Method and apparatus for calculating effective memory addresses'19995,854,914'Mechanism to improved execution of misaligned loads'19985,852,726'Method and apparatus for executing two types of instructions that specify registers of a shared logical register file in a stack and a non-stack referenced manner'19985,835,748'Method for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file'19985,826,094'Register alias table update to indicate architecturally visible state'19985,826,109'Method and apparatus for performing multiple load operations to the same memory location in a computer system'19985,819,079'Instruction fetch on demand for uncacheable memory which avoids memory mapped I/O side effects in a processor with speculative instruction fetch'19985,809,271'Method and apparatus for changing flow of control in a processor'19985,796,637'Apparatus and method for filtering event signals'19985,778,407'Methods and apparatus for determining operating characteristics of a memory element based on its physical location'19985,778,245'Method and apparatus for dynamic allocation of multiple buffers in a processor'19985,751,986'Computer system with self-consistent ordering mechanism'19985,751,983'Out-of-order processor with a memory subsystem which handles speculatively dispatched load operations'19985,751,996'Method and apparatus for processing memory-type information within a microprocessor'19985,749,084'Address generation unit with segmented addresses in a microprocessor'19985,748,937'Computer system that maintains processor ordering consistency by snooping an external bus for conflicts during out of order execution of memory access instructions'19985,740,393'Instruction pointer limits in processor that performs speculative out-of-order instruction execution'19985,729,728'Method and apparatus for predicting, clearing and redirecting unpredicted changes in instruction flow in a microprocessor'19985,727,176'Data processor with circuitry for handling pointers associated with a register exchange operation'19985,724,536'Method and apparatus for blocking execution of and storing load operations during their execution'19985,724,527'Fault-tolerant boot strap mechanism for a multiprocessor system'19985,721,857'Method and apparatus for saving the effective address of floating point memory operations in an out-of-order microprocessor'19985,721,855'Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer'19985,717,882'Method and apparatus for dispatching and executing a load operation to memory'19985,708,843'Method and apparatus for handling code segment violations in a computer system'19985,701,508'Executing different instructions that cause different data type operations to be performed on single logical register file'19975,694,589'Instruction breakpoint detection apparatus for use in an out-of-order microprocessor'19975,694,574'Method and apparatus for performing load operations in a computer system'19975,687,338'Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor'19975,680,572'Cache memory system having data and tag arrays and multi-purpose buffer assembly with multiple line buffers'19975,671,444'Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers'19975,664,137'Method and apparatus for executing and dispatching store operations in a computer system'19975,636,374'Method and apparatus for performing operations based upon the addresses of microinstructions'19975,630,075'Write combining buffer for sequentially addressed partial line operations originating from a single instruction'19975,627,985'Speculative and committed resource files in an out-of-order processor'19975,619,664'Processor with architecture for improved pipelining of arithmetic instructions by forwarding redundant intermediate data forms'19975,615,385'Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming'19975,613,132'Integer and floating point register alias table within processor device'19975,613,083'Translation lookaside buffer that is non-blocking in response to a miss for use within a microprocessor capable of processing speculative instructions'19975,606,670'Method and apparatus for signalling a store buffer to output buffered store data for a load operation on an out-of-order execution computer system'19975,604,878'Method and apparatus for avoiding writeback conflicts between execution units sharing a common writeback path'19975,590,297'Address generation unit with segmented addresses in a mircroprocessor'19965,588,126'Methods and apparatus for fordwarding buffered store data on an out-of-order execution computer system'19965,584,001'Branch target buffer for dynamically predicting branch instruction outcomes using a predicted branch history'19965,584,038'Entry allocation in a circular buffer using wrap bits indicating whether a queue of the circular buffer has been traversed'19965,584,037'Entry allocation in a circular buffer'19965,577,200'Method and apparatus for loading and storing misaligned data on an out-of-order execution computer system'19965,574,942'Hybrid execution unit for complex microprocessor'19965,564,056'Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming'19965,564,111'Method and apparatus for implementing a non-blocking translation lookaside buffer'19965,561,814'Methods and apparatus for determining memory operating characteristics for given memory locations via assigned address ranges'19965,548,776'N-wide bypass for data dependencies within register alias table'19965,546,597'Ready selection of data dependent instructions using multi-cycle cams in a processor performing out-of-order instruction execution'19965,526,510'Method and apparatus for implementing a single clock cycle line replacement in a data cache unit'19965,524,262'Apparatus and method for renaming registers in a processor and resolving data dependencies thereof'19965,517,651'Method and apparatus for loading a segment register in a microprocessor capable of operating in multiple modes'19965,499,352'Floating point register alias table FXCH and retirement floating point register array'19965,497,493'High byte right-shift apparatus with a register alias table'19965,471,633'Idiom recognizer within a register alias table'19955,463,745'Methods and apparatus for determining the next instruction pointer in an out-of-order execution computer system'19955,452,426'Coordinating speculative and committed state register source data and immediate source data in a processor'19955,446,912'Partial width stalls within register alias table'19955,434,987'Method and apparatus for preventing incorrect fetching of an instruction of a self-modifying code sequence with dependency on a bufered store'19955,420,991'Apparatus and method for maintaining processing consistency in a computer system having multiple processors'19955,404,473'Apparatus and method for handling string operations in a pipelined processor'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995–2017Patents assigned to INTEL CORP (91)· patent assignee history
1995–2017Based in Hillsboro, OR, US· patent location history
1998–2007Based in Madison, WI, US· patent location history
2003–2018Based in Portland, OR, US· patent location history
2008Based in San Jose, CA, US· patent location history
2014–2018Patents assigned to ELWHA LLC (19)· patent assignee history
2014–2017Patents assigned to GERRITY DANIEL A (13)· patent assignee history
2014–2017Patents assigned to TEGREENE CLARENCE T (12)· patent assignee history
2014–2016Patents assigned to GLEW ANDREW F (8)· patent assignee history
2020Based in Santa Clara, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 91 | 1995–2017 |
| ELWHA LLC | 19 | 2014–2018 |
| GERRITY DANIEL A | 13 | 2014–2017 |
| TEGREENE CLARENCE T | 12 | 2014–2017 |
| GLEW ANDREW Fself | 8 | 2014–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hillsboro, OR, US | 105 | 1995–2017 |
| Madison, WI, US | 7 | 1998–2007 |
| Portland, OR, US | 6 | 2003–2018 |
| Santa Clara, California, US | 1 | 2020 |
| San Jose, California, US | 1 | 2008 |