Inventor
Sailesh Merchant
Inventor
Orlando, FL, US
Overview
Patents· 135 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1031%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1020%
H10DInorganic electric semiconductor devices19%
H10BElectronic memory devices4%
B24BMachines, devices, or processes for grinding or polishing4%
C23CCoating metallic material4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
C09GPolishing compositions2%
G01RMeasuring electric variables2%
C09KMaterials for miscellaneous applications, not provided for elsewhere1%
PatentTitleYear
9,613,847'Integration of shallow trench isolation and through-substrate vias into integrated circuit designs'20179,054,064'Stacked interconnect heat sink'20158,987,137'Method of fabrication of through-substrate vias'20158,854,115'Preventing electronic device counterfeits'20148,742,535'Integration of shallow trench isolation and through-substrate vias into integrated circuit designs'20148,507,317'Solder bump structure for flip chip semiconductor devices and method of manufacturing therefore'20138,492,911'Stacked interconnect heat sink'20138,319,343'Routing under bond pad for the replacement of an interconnect layer'20127,973,544'Thermal monitoring and management of integrated circuits'20117,952,206'Solder bump structure for flip chip semiconductor devices and method of manufacture therefore'20117,948,914'Power learning security in wireless routers'20117,804,291'Semiconductor test device with heating circuit'20107,777,333'Structure and method for fabricating flip chip devices'20107,727,894'Formation of an integrated circuit structure with reduced dishing in metallization levels'20107,678,639'Inductor formed in an integrated circuit'20107,566,964'Aluminum pad power bus and signal routing for integrated circuit devices utilizing copper technology interconnect structures'20097,541,238'Inductor formed in an integrated circuit'20097,429,502'Integrated circuit device incorporating metallurgical bond to enhance thermal conduction to a heat sink'20087,397,103'Semiconductor with damage detection circuitry'20087,388,395'Test semiconductor device and method for determining Joule heating effects in such a device'20087,328,830'Structure and method for bonding to copper interconnect structures'20087,327,029'Integrated circuit device incorporating metallurigical bond to enhance thermal conduction to a heat sink'20087,301,107'Semiconductor device having reduced intra-level and inter-level capacitance'20077,301,231'Reinforced bond pad for a semiconductor device'20077,221,173'Method and structures for testing a semiconductor wafer prior to performing a flip chip bumping process'20077,135,733'Capacitor for integration with copper damascene processes and a method of manufacture therefore'20067,115,985'Reinforced bond pad for a semiconductor device'20067,071,563'Barrier layer for interconnect structures of a semiconductor wafer and method for depositing the barrier layer'20067,068,139'Inductor formed in an integrated circuit'20067,061,264'Test semiconductor device and method for determining Joule heating effects in such a device'20067,005,375'Method to avoid copper contamination of a via or dual damascene structure'20066,982,226'Method of fabricating a contact with a post contact plug anneal'20066,960,836'Reinforced bond pad'20056,890,827'Method of fabricating a silicon on insulator transistor structure for imbedded DRAM'20056,869,873'Copper silicide passivation for improved reliability'20056,790,757'Wire bonding method for copper interconnects in semiconductor devices'20046,784,478'Junction capacitor structure and fabrication method therefor in a dual damascene process'20046,750,145'Method of eliminating agglomerate particles in a polishing slurry'20046,730,601'Methods for fabricating a metal-oxide-metal capacitor'20046,730,600'Method of dry etching a semiconductor device in the absence of a plasma'20046,727,588'Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics'20046,720,261'Method and system for eliminating extrusions in semiconductor vias'20046,720,604'Capacitor for an integrated circuit'20046,703,712'Microelectronic device layer deposited with multiple electrolytes'20046,699,372'Method of coil preparation for ionized metal plasma process and method of manufacturing integrated circuits'20046,686,662'Semiconductor device barrier layer'20046,599,837'Chemical mechanical polishing composition and method of polishing metal layers using same'20036,585,830'Method for cleaning tungsten from deposition wall chambers'20036,573,183'Method and apparatus for controlling contamination during the electroplating deposition of metals onto a semiconductor wafer surface'20036,541,394'Method of making a graded grown, high quality oxide layer for a semiconductor device'20036,537,135'Curvilinear chemical mechanical planarization device and method'20036,532,489'Electronic mail alerting system and method with user options'20036,525,358'Capacitor having the lower electrode for preventing undesired defects at the surface of the metal plug'20036,524,957'Method of forming in-situ electroplated oxide passivating film for corrosion inhibition'20036,498,364'Capacitor for integration with copper damascene processes'20026,495,875'Method of forming metal oxide metal capacitors using multi-step rapid material thermal process and a device formed thereby'20026,492,712'High quality oxide for use in integrated circuits'20026,472,304'Wire bonding to copper'20026,471,925'Method for treating an effluent gas during semiconductor processing'20026,458,016'Polishing fluid, polishing method, semiconductor device and semiconductor device fabrication method'20026,458,289'CMP slurry for polishing semiconductor wafers and related methods'20026,455,418'Barrier for copper metallization'20026,440,849'Microstructure control of copper interconnects'20026,440,852'Integrated circuit including passivated copper interconnection lines and associated manufacturing methods'20026,436,830'CMP system for polishing semiconductor wafers and related method'20026,410,419'Silicon carbide barrier layers for porous low dielectric constant materials'20026,410,986'Multi-layered titanium nitride barrier structure'20026,403,415'Semiconductor device having a metal barrier layer for a dielectric material having a high dielectric constant and a method of manufacture thereof'20026,375,541'Polishing fluid polishing method semiconductor device and semiconductor device fabrication method'20026,373,087'Methods of fabricating a metal-oxide-metal capacitor and associated apparatuses'20026,368,200'Polishing pads from closed-cell elastomer foam'20026,364,744'CMP system and slurry for polishing semiconductor wafers and related method'20026,365,511'Tungsten silicide nitride as a barrier for high temperature anneals to improve hot carrier reliability'20026,365,327'Process for manufacturing in integrated circuit including a dual-damascene structure and an integrated circuit'20026,358,790'Method of making a capacitor'20026,359,339'Multi-layered metal silicide resistor for Si Ic\'s'20026,355,184'Method of eliminating agglomerate particles in a polishing slurry'20026,348,393'Capacitor in an integrated circuit and a method of manufacturing an integrated circuit'20026,340,827'Diffusion barrier for use with high dielectric constant materials and electronic devices incorporating same'20026,339,246'Tungsten silicide nitride as an electrode for tantalum pentoxide devices'20026,335,557'Metal silicide as a barrier for MOM capacitors in CMOS technologies'20026,331,484'Titanium-tantalum barrier layer film and method for forming the same'20016,331,460'Method of fabricating a mom capacitor having a metal silicide barrier'20016,323,044'Method of forming capacitor having the lower metal electrode for preventing undesired defects at the surface of the metal plug'20016,323,537'Capacitor for an integrated circuit'20016,323,078'Method of forming metal oxide metal capacitors using multi-step rapid thermal process and a device formed thereby'20016,319,095'Colloidal suspension of abrasive particles containing magnesium as CMP slurry'20016,320,244'Integrated circuit device having dual damascene capacitor'20016,320,238'Gate structure for integrated circuit fabrication'20016,319,837'Technique for reducing dishing in Cu-based interconnects'20016,313,021'PMOS device having a layered silicon gate for improved silicide integrity and enhanced boron penetration resistance'20016,313,025'Process for manufacturing an integrated circuit including a dual-damascene structure and an integrated circuit'20016,294,468'Method of chemical vapor depositing tungsten films'20016,291,848'Integrated circuit capacitor including anchored plugs'20016,288,449'Barrier for copper metallization'20016,287,970'Method of making a semiconductor with copper passivating film'20016,281,110'Method for making an integrated circuit including deutrium annealing of metal interconnect layers'20016,281,129'Corrosion-resistant polishing pad conditioner'20016,264,536'Reducing polish platen corrosion during integrated circuit fabrication'20016,255,688'Capacitor having aluminum alloy bottom plate'20016,235,594'Methods of fabricating an integrated circuit device with composite oxide dielectric'20016,218,255'Method of making a capacitor'20016,180,518'Method for forming vias in a low dielectric constant material'20016,169,036'Method for cleaning via openings in integrated circuit manufacturing'20016,168,991'DRAM capacitor including Cu plug and Ta barrier and method of forming'20016,157,082'Semiconductor device having aluminum contacts or vias and method of manufacture therefor'20006,153,452'Method of manufacturing semiconductor devices having improved polycide integrity through introduction of a silicon layer within the polycide structure'20006,147,388'Polycide gate structure with intermediate barrier'20006,136,159'Method for depositing metal'20006,130,150'Method of making a semiconductor device with barrier and conductor protection'20006,119,921'Bonding of aluminum oxide components to silicon substrates'20006,114,234'Method of making a semiconductor with copper passivating film'20006,103,607'Manufacture of MOSFET devices'20006,103,586'Method for making integrated circuit capacitor including anchored plugs'20006,100,587'Silicon carbide barrier layers for porous low dielectric constant materials'20006,071,808'Method of passivating copper interconnects in a semiconductor'20006,034,405'Bonding of aluminum oxide components to silicons substrates'20006,028,359'Integrated circuit having amorphous silicide layer in contacts and vias and method of manufacture therefor'20005,994,221'Method of fabricating aluminum-indium (or thallium) vias for ULSI metallization and interconnects'19995,981,403'Layered silicon nitride deposition process'19995,972,179'Silicon IC contacts using composite TiN barrier layer'19995,935,396'Method for depositing metal'19995,913,146'Semiconductor device having aluminum contacts or vias and method of manufacture therefor'19995,902,504'Systems and methods for determining semiconductor wafer temperature and calibrating a vapor deposition device'19995,858,873'Integrated circuit having amorphous silicide layer in contacts and vias and method of manufacture thereof'19995,846,871'Integrated circuit fabrication'19985,807,760'Method of despositing an aluminum-rich layer'19985,798,300'Method for forming conductors in integrated circuits'19985,693,561'Method of integrated circuit fabrication including a step of depositing tungsten'19975,641,994'Multilayered A1-alloy structure for metal conductors'19975,599,739'Barrier layer treatments for tungsten plug'19975,561,083'Method of making multilayered Al-alloy structure for metal conductors'19965,523,259'Method of forming metal layers formed as a composite of sub-layers using Ti texture control layer'19965,489,552'Multiple layer tungsten deposition process'19965,461,005'Method of forming silicide in integrated circuit manufacture'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995Based in Northampton, PA, US· patent location history
1996–2003Patents assigned to LUCENT TECHNOLOGIES INC (35)· patent assignee history
1996–2007Based in Orlando, FL, US· patent location history
1998–1999Based in Bethlehem, PA, US· patent location history
2001–2011Patents assigned to AGERE SYSTEMS INC (46)· patent assignee history
2001–2004Patents assigned to AGERE SYST GUARDIAN CORP (41)· patent assignee history
2005–2009Based in Breinigsville, PA, US· patent location history
2006–2017Based in Macungie, PA, US· patent location history
2012–2015Patents assigned to BACHMAN MARK A (5)· patent assignee history
2013–2017Patents assigned to LSI CORP (6)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| AGERE SYSTEMS INC | 46 | 2001–2011 |
| AGERE SYST GUARDIAN CORP | 41 | 2001–2004 |
| LUCENT TECHNOLOGIES INC | 35 | 1996–2003 |
| LSI CORP | 6 | 2013–2017 |
| BACHMAN MARK A | 5 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Orlando, Florida, US | 104 | 1996–2007 |
| Macungie, Pennsylvania, US | 25 | 2006–2017 |
| Breinigsville, Pennsylvania, US | 3 | 2005–2009 |
| Bethlehem, Pennsylvania, US | 2 | 1998–1999 |
| Northampton, Pennsylvania, US | 1 | 1995 |