Inventor

Pratyush Kamal

Inventor

San Diego, CA, US

Overview

15→

Patents

2013–2018

Patent span

Electricity

Primary field (CPC H)

Patents· 15 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices26%

H01LSemiconductor devices23%

G06FElectric digital data processing17%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%

H03KPulse technique11%

G11CStatic stores4%

H04LTransmission of digital information, e.g. telegraphic communication2%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h102%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%

PatentTitleYear

10,121,743Power distribution networks for a three-dimensional (3D) integrated circuit (IC) (3DIC)2018 10,062,680Silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) standard library cell circuits having a gate back-bias rail(s), and related systems and methods2018 9,929,733'Connection propagation for inter-logical block connections in integrated circuits'2018 9,754,923'Power gate placement techniques in three-dimensional (3D) integrated circuits (ICs) (3DICs)'2017 9,537,471'Three dimensional logic circuit'2017 9,508,615'Clock tree synthesis for low cost pre-bond testing of 3D integrated circuits'2016 9,213,358'Monolithic three dimensional (3D) integrated circuit (IC) (3DIC) cross-tier clock skew management systems, methods and related components'2015 9,147,438'Monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) with vertical memory components, related systems and methods'2015 9,123,721'Placement of monolithic inter-tier vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespace'2015 9,093,995'Length-of-diffusion protected circuit and method of design'2015 9,053,960'Decoupling capacitor for integrated circuit'2015 9,013,235'Monolithic three dimensional (3D) flip-flops with minimal clock skew and related systems and methods'2015 8,836,040'Shared-diffusion standard cell architecture'2014 8,610,176'Standard cell architecture using double poly patterning for multi VT devices'2013 8,584,075'Method and apparatus for characterizing and reducing proximity effect on cell electrical characteristics'2013

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2013–2018Patents assigned to QUALCOMM INC (15)· patent assignee history

2013Patents assigned to KAMAL PRATYUSH (2)· patent assignee history

2013Patents assigned to PATEL PRAYAG B (2)· patent assignee history

2013Patents assigned to CHIDAMBARAM PR (1)· patent assignee history

2013Patents assigned to DATTA ANIMESH (1)· patent assignee history

2013–2018Based in San Diego, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
QUALCOMM INC	15	2013–2018
KAMAL PRATYUSHself	2	2013
PATEL PRAYAG B	2	2013
CHIDAMBARAM PR	1	2013
DATTA ANIMESH	1	2013

Locations

Location	Patents	Span
San Diego, California, US	15	2013–2018