Inventor
Matthias Lehr
Inventor
Dresden, DE
Overview
Patents· 67 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1040%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%
G06FElectric digital data processing7%
H01LSemiconductor devices7%
H10DInorganic electric semiconductor devices6%
Y10TTechnical subjects covered by former us classification5%
C07DHeterocyclic compounds2%
H04LTransmission of digital information, e.g. telegraphic communication2%
A61PSpecific therapeutic activity of chemical compounds or medicinal preparations2%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes2%
PatentTitleYear
10,942,001Stow pin actuator202110,768,946Edge configuration of software systems for manufacturing202010,713,270Emerging issue detection and analysis202010,607,947Semiconductor device comprising a die seal including long via lines202010,014,234Semiconductor device comprising a die seal including long via lines20189,898,572'Metal line layout based on line shifting'20189,524,239'Self service propagation of custom extension fields into web services'20169,450,042'Integrated circuits with metal-insulator-metal (MIM) capacitors and methods for fabricating same'20169,324,631'Semiconductor device including a stress buffer material formed above a low-k metallization system'20169,244,697'Stable anchors in user interface to support life cycle extensions'20169,136,234'Semiconductor device with improved metal pillar configuration'20159,054,112'Semiconductor device comprising a die seal having an integrated alignment mark'20158,920,027'Assessing thermal mechanical characteristics of complex semiconductor devices by integrated heating systems'20148,924,565'Transport of customer flexibility changes in a multi-tenant environment'20148,863,005'Propagating business object extension fields from source to target'20148,841,140'Technique for forming a passivation layer without a terminal metal'20148,828,888'Protection of reactive metal surfaces of semiconductor devices during shipping by providing an additional protection layer'20148,819,075'Facilitation of extension field usage based on reference field usage'20148,575,029'Technique for forming metal lines in a semiconductor by adapting the temperature dependence of the line resistance'20138,561,446'Method and device for fabricating bonding wires on the basis of microelectronic manufacturing techniques'20138,501,545'Reduction of mechanical stress in metal stacks of sophisticated semiconductor devices during die-substrate soldering by an enhanced cool down regime'20138,489,640'Field extensibility using generic boxed components'20138,482,123'Stress reduction in chip packaging by using a low-temperature chip-package connection regime'20138,479,578'Assessing metal stack integrity in sophisticated semiconductor devices by mechanically stressing die contacts'20138,450,206'Method of forming a semiconductor device including a stress buffer material formed above a low-k metallization system'20138,404,577'Semiconductor device having a grain orientation layer'20138,392,573'Transport of customer flexibility changes in a multi-tenant environment'20138,329,577'Method of forming an alloy in an interconnect structure to increase electromigration resistance'20128,283,247'Semiconductor device including a die region designed for aluminum-free solder bump connection and a test structure designed for aluminum-free wire bonding'20128,216,880'Wire bonding on reactive metal surfaces of a metallization of a semiconductor device by providing a protection layer'20128,114,688'Method and semiconductor structure for monitoring etch characteristics during fabrication of vias of interconnect structures'20128,062,982'High yield plasma etch process for interlayer dielectrics'20118,058,731'Technique for forming metal lines in a semiconductor by adapting the temperature dependence of the line resistance'20118,053,354'Reduced wafer warpage in semiconductors by stress engineering in the metallization system'20118,043,956'Wire bonding on reactive metal surfaces of a metallization of a semiconductor device by providing a protective layer'20118,039,958'Semiconductor device including a reduced stress configuration for metal pillars'20118,039,400'Reducing contamination of semiconductor substrates during BEOL processing by performing a deposition/etch cycle during barrier deposition'20117,982,313'Semiconductor device including stress relaxation gaps for enhancing chip package interaction stability'20117,867,917'Etch stop layer for a metallization layer with enhanced adhesion, etch selectivity and hermeticity'20117,838,359'Technique for forming contact insulation layers and silicide regions with different characteristics'20107,829,357'Method and test structure for monitoring CMP processes in metallization layers of semiconductor devices'20107,829,889'Method and semiconductor structure for monitoring etch characteristics during fabrication of vias of interconnect structures'20107,713,815'Semiconductor device including a vertical decoupling capacitor'20107,678,699'Method of forming an insulating capping layer for a copper metallization layer by using a silane reaction'20107,608,633'Heteroaryl-substituted acetone derivatives as inhibitors of phospholipase A2 '20097,592,258'Metallization layer of a semiconductor device having differently thick metal lines and a method of forming the same'20097,569,937'Technique for forming a copper-based contact layer without a terminal metal'20097,550,396'Method for reducing resist poisoning during patterning of silicon nitride layers in a semiconductor device'20097,491,555'Method and semiconductor structure for monitoring the fabrication of interconnect structures and contacts in a semiconductor device'20097,491,638'Method of forming an insulating capping layer for a copper metallization layer'20097,476,626'Etch stop layer for a metallization layer with enhanced etch selectivity and hermeticity'20097,416,992'Method of patterning a low-k dielectric using a hard mask'20087,375,032'Semiconductor substrate thinning method for manufacturing thinned die'20087,306,976'Technique for enhancing thermal and mechanical characteristics of an underfill material of a substrate/die assembly'20076,803,612'Integrated circuit having electrical connecting elements'20046,737,748'Stacked via with specially designed landing pad for integrated semiconductor structures'20046,716,678'Method for producing an antifuse and antifuse for the selective electrical connection of adjacent conductive regions'20046,635,567'Method of producing alignment marks'20036,559,547'Patterning of content areas in multilayer metalization configurations of semiconductor components'20036,559,067'Method for patterning an organic antireflection layer'20036,458,631'Method for fabricating an integrated circuit, in particular an antifuse'20026,455,435'Method for fabricating a wiring plane on a semiconductor chip with an antifuse'20026,429,503'Connection element in an integrated circuit having a layer structure disposed between two conductive structures'20026,387,792'Method of fabricating a dielectric antifuse structure'20026,337,263'Method for improving the quality of metal conductor tracks on semiconductor structures'20026,310,217'Acylpyrroledicarboxylic acids and acylindoledicarboxylic acids and their derivatives as inhibitors of cytosolic phospholipase A2'20015,260,451'Substituted pyrrole compounds and use thereof in pharmaceutical compositions'1993Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1993–2001Based in Munich, DE· patent location history
2002–2004Patents assigned to INFINEON TECHNOLOGIES AG (11)· patent assignee history
2002–2020Based in Dresden, DE· patent location history
2007–2014Patents assigned to ADVANCED MICRO DEVICES INC (21)· patent assignee history
2009Based in Havixbeck, DE· patent location history
2010–2020Patents assigned to GLOBALFOUNDRIES INC (22)· patent assignee history
2011–2016Patents assigned to LEHR MATTHIAS (25)· patent assignee history
2013–2016Patents assigned to SCHLARB UWE (7)· patent assignee history
2013–2020Based in Weinheim, DE· patent location history
2021Based in King George, VA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| LEHR MATTHIASself | 25 | 2011–2016 |
| GLOBALFOUNDRIES INC | 22 | 2010–2020 |
| ADVANCED MICRO DEVICES INC | 21 | 2007–2014 |
| INFINEON TECHNOLOGIES AG | 11 | 2002–2004 |
| SCHLARB UWE | 7 | 2013–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Dresden, DE | 54 | 2002–2020 |
| Weinheim, DE | 9 | 2013–2020 |
| Munich, DE | 2 | 1993–2001 |
| King George, Virginia, US | 1 | 2021 |
| Havixbeck, DE | 1 | 2009 |