Inventor
Aaron D. Lilak
Inventor
Beaverton, OR, US
Overview
Patents· 26 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices29%
H10DInorganic electric semiconductor devices29%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%
B82YSpecific uses or applications of nanostructures6%
H10BElectronic memory devices6%
G11CStatic stores1%
PatentTitleYear
11,107,811Metallization structures under a semiconductor device layer202111,107,924Systems and methods to reduce FinFET gate capacitance202111,075,198Stacked transistor architecture having diverse fin geometry202111,075,202Bottom fin trim isolation aligned with top gate for stacked device architectures202111,075,119Vertically stacked transistors in a pin202111,049,861Method, device and system to provide capacitance for a dynamic random access memory cell202111,011,537Vertical interconnect methods for stacked device architectures using direct self assembly with high operational parallelization and improved scalability202110,991,696Vertically stacked devices with self-aligned regions formed by direct self assembly (DSA) processing202110,978,590Methods and apparatus to remove epitaxial defects in semiconductors202110,937,665Methods and apparatus for gettering impurities in semiconductors202110,910,405Backside fin recess control with multi-HSI option202110,892,326Removal of a bottom-most nanowire from a nanowire device stack202110,892,335Device isolation by fixed charge202110,861,870Inverted staircase contact for density improvement to 3D stacked devices202010,784,358Backside contact structures and fabrication for metal on both sides of devices202010,636,907Deep EPI enabled by backside reveal for stress enhancement and contact202010,600,810Backside fin recess control with multi-hsi option202010,573,715Backside isolation for integrated circuit202010,546,873Integrated circuit with stacked transistor devices202010,529,827Long channel MOS transistors for low leakage applications on a short channel CMOS chip202010,497,781Methods for doping a sub-fin region of a semiconductor structure by backside reveal and associated devices201910,468,489Isolation structures for an integrated circuit element and method of making same201910,026,829Semiconductor device with isolated body portion20189,608,059'Semiconductor device with isolated body portion'20177,129,533'High concentration indium fluorine retrograde wells'20066,838,329'High concentration indium fluorine retrograde wells'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2021Patents assigned to INTEL CORP (26)· patent assignee history
2005–2006Based in Hillsboro, OR, US· patent location history
2017Patents assigned to CAPPELLANI ANNALISA (1)· patent assignee history
2017Patents assigned to CEA STEPHEN M (1)· patent assignee history
2017Patents assigned to GHANI TAHIR (1)· patent assignee history
2017Patents assigned to GOMEZ HARRY (1)· patent assignee history
2017–2021Based in Beaverton, OR, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 26 | 2005–2021 |
| CAPPELLANI ANNALISA | 1 | 2017 |
| CEA STEPHEN M | 1 | 2017 |
| GHANI TAHIR | 1 | 2017 |
| GOMEZ HARRY | 1 | 2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Beaverton, OR, US | 24 | 2017–2021 |
| Hillsboro, OR, US | 2 | 2005–2006 |