Inventor

Michiharu Matsui

Inventor

Fujisawa, JP

Overview

1996–2015

Patent span

Electricity

Primary field (CPC H)

Patents· 25 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Bprimary

H10BElectronic memory devices42%

H10DInorganic electric semiconductor devices30%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1021%

G11CStatic stores5%

H01LSemiconductor devices2%

PatentTitleYear

9,059,300'Nonvolatile semiconductor memory device having element isolating region of trench type'2015 8,421,143'Nonvolatile semiconductor memory device having element isolating region of trench type'2013 8,405,139'Nonvolatile semiconductor memory device having element isolating region of trench type'2013 7,939,406'Nonvolatile semiconductor memory device having element isolating region of trench type'2011 7,573,092'Nonvolatile semiconductor memory device having element isolating region of trench type'2009 7,538,380'Nonvolatile semiconductor memory device having element isolating region of trench type'2009 7,504,294'Method of manufacturing an electrically erasable programmable read-only memory (EEPROM)'2009 7,449,745'Nonvolatile semiconductor memory device having element isolating region of trench type'2008 7,417,281'Semiconductor device with a selection gate and a peripheral gate'2008 7,382,016'Semiconductor device and method of manufacturing the same'2008 7,352,027'Nonvolatile semiconductor memory device having element isolating region of trench type'2008 7,348,627'Nonvolatile semiconductor memory device having element isolating region of trench type'2008 7,049,653'Nonvolatile semiconductor memory device having element isolating region of trench type'2006 7,045,423'Non-volatile semiconductor memory device with multi-layer gate structure'2006 6,998,673'Semiconductor device and method of manufacturing the same'2006 6,969,660'Method of manufacturing a semiconductor device with trench isolation between two regions having different gate insulating films'2005 6,927,449'Nonvolatile semiconductor memory device having element isolating region of trench type'2005 6,902,976'Semiconductor device and method of manufacturing the same'2005 6,894,341'Semiconductor device and manufacturing method'2005 6,853,029'Non-volatile semiconductor memory device with multi-layer gate structure'2005 6,844,590'Semiconductor device with trench isolation between two regions having different gate insulating films'2005 6,835,978'Nonvolatile semiconductor memory device having element isolating region of trench type'2004 6,661,052'Semiconductor device and method of manufacturing the same'2003 6,441,427'NOR-type flash memory and method for manufacturing the same'2002 5,559,736'Non-volatile semiconductor memory device capable of preventing excessive-writing'1996

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1996–2015Patents assigned to TOSHIBA KK (25)· patent assignee history

1996–2002Based in Yokohama, JP· patent location history

2003–2015Based in Fujisawa, JP· patent location history

2013Patents assigned to KAMIGAICHI TAKESHI (2)· patent assignee history

2013Patents assigned to MATSUI MICHIHARU (2)· patent assignee history

2013Patents assigned to MORI SEIICHI (2)· patent assignee history

2013Patents assigned to SHIROTA RIICHIRO (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TOSHIBA KK	25	1996–2015
KAMIGAICHI TAKESHI	2	2013
MATSUI MICHIHARUself	2	2013
MORI SEIICHI	2	2013
SHIROTA RIICHIRO	2	2013

Locations

Location	Patents	Span
Fujisawa, JP	23	2003–2015
Yokohama, JP	2	1996–2002