Inventor
Juergen Koehl
Inventor
Weil am Rhein, DE
Overview
Patents· 38 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing60%
Y02PClimate change mitigation technologies in the production or processing of goods10%
H10DInorganic electric semiconductor devices6%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
G01RMeasuring electric variables4%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices4%
H03KPulse technique4%
G11CStatic stores2%
H04LTransmission of digital information, e.g. telegraphic communication2%
H04QSelecting2%
PatentTitleYear
9,256,430'Instruction scheduling approach to improve processor performance'20168,972,961'Instruction scheduling approach to improve processor performance'20158,935,685'Instruction scheduling approach to improve processor performance'20158,762,919'Circuit macro placement using macro aspect ratio based on ports'20148,522,187'Method and data processing system to optimize performance of an electric circuit design, data processing program and computer program product'20138,513,663'Signal repowering chip for 3-dimensional integrated circuit'20138,418,090'Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool'20138,234,594'Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same'20128,136,066'Apparatus and computer program product for semiconductor yield estimation'20128,132,129'Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool'20128,056,037'Method for validating logical function and timing behavior of a digital circuit decision'20118,015,527'Routing of wires of an electronic circuit'20118,010,925'Method and system for placement of electric circuit components in integrated circuit design'20118,010,916'Test yield estimate for semiconductor products created from a library'20117,996,808'Computer readable medium, system and associated method for designing integrated circuits with loop insertions'20117,984,394'Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same'20117,960,836'Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same'20117,962,877'Port assignment in hierarchical designs by abstracting macro logic'20117,961,932'Method and apparatus for manufacturing diamond shaped chips'20117,962,881'Via structure to improve routing of wires within an integrated circuit'20117,886,245'Structure for optimizing the signal time behavior of an electronic circuit design'20117,865,855'Method and system for generating a layout for an integrated electronic circuit'20117,844,931'Method and computer system for optimizing the signal time behavior of an electronic circuit design'20107,755,408'Redundancy in signal distribution trees'20107,526,743'Method for routing data paths in a semiconductor chip with a plurality of layers'20097,496,874'Semiconductor yield estimation'20097,490,310'Method for creating a layout for an electronic circuit'20097,487,476'Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool'20097,398,485'Yield optimization in router for systematic defects'20087,392,497'Regular routing for deep sub-micron chip design'20087,386,815'Test yield estimate for semiconductor products created from a library'20087,336,115'Redundancy in signal distribution trees'20087,308,669'Use of redundant routes to increase the yield and reliability of a VLSI layout'20077,289,659'Method and apparatus for manufacturing diamond shaped chips'20077,206,308'Method of providing a non-blocking routing network'20077,145,873'Switching arrangement and method with separated output buffers'20066,904,584'Method and system for placing logic nodes based on an estimated wiring congestion'20056,218,631'Structure for reducing cross-talk in VLSI circuits and method of making same using filled channels to minimize cross-talk'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2016Patents assigned to IBM (37)· patent assignee history
2001–2013Based in Weil am Rhein, DE· patent location history
2009Based in Well un Schoenbuch, DE· patent location history
2012–2015Patents assigned to KOEHL JUERGEN (9)· patent assignee history
2012–2013Patents assigned to HIBBELER JASON D (4)· patent assignee history
2012–2013Patents assigned to BICKFORD JEANNE P (3)· patent assignee history
2012–2013Patents assigned to BUEHLER MARKUS (2)· patent assignee history
2013Based in Nuremberg, DE· patent location history
2014–2016Based in Boeblingen, DE· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 37 | 2001–2016 |
| KOEHL JUERGENself | 9 | 2012–2015 |
| HIBBELER JASON D | 4 | 2012–2013 |
| BICKFORD JEANNE P | 3 | 2012–2013 |
| BUEHLER MARKUS | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Weil am Rhein, DE | 32 | 2001–2013 |
| Boeblingen, DE | 4 | 2014–2016 |
| Nuremberg, DE | 1 | 2013 |
| Well un Schoenbuch, DE | 1 | 2009 |