Inventor

Jude A. Rivers

Inventor

Cortlandt Manor, NY, US

Overview

2004–2019

Patent span

Physics

Primary field (CPC G)

Patents· 43 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing50%

G11CStatic stores7%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use7%

Y10TTechnical subjects covered by former us classification7%

H01LSemiconductor devices4%

H05KPrinted circuits4%

A61GTransport, personal conveyances, or accommodation specially adapted for patients or disabled persons3%

A61HPhysical therapy apparatus, e.g. devices for locating or stimulating reflex points in the body3%

G01RMeasuring electric variables3%

PatentTitleYear

10,216,557Method and apparatus for monitoring and enhancing on-chip microprocessor reliability2019 9,740,496'Processor with memory-embedded pipeline for table-driven computation'2017 9,740,497'Processor with memory-embedded pipeline for table-driven computation'2017 9,431,084'Determining and storing bit error rate relationships in spin transfer torque magnetoresistive random-access memory (STT-MRAM)'2016 9,418,721'Determining and storing bit error rate relationships in spin transfer torque magnetoresistive random-access memory (STT-MRAM)'2016 9,406,368'Dynamic temperature adjustments in spin transfer torque magnetoresistive random-access memory (STT-MRAM)'2016 9,390,989'Enhanced modularity in heterogeneous 3D stacks'2016 9,373,557'Enhanced modularity in heterogeneous 3D stacks'2016 9,351,899'Dynamic temperature adjustments in spin transfer torque magnetoresistive random-access memory (STT-MRAM)'2016 9,122,513'Method and apparatus for efficient execution of concurrent processes on a multithreaded message passing system'2015 9,116,738'Method and apparatus for efficient execution of concurrent processes on a multithreaded message passing system'2015 8,796,047'Semiconductor chip repair by stacking of a base semiconductor chip and a repair semiconductor chip'2014 8,679,861'Semiconductor chip repair by stacking of a base semiconductor chip and a repair semiconductor chip'2014 8,677,613'Enhanced modularity in heterogeneous 3D stacks'2014 8,595,731'Low overhead dynamic thermal management in many-core cluster architecture'2013 8,589,762'Adaptive multi-bit error correction in endurance limited memories'2013 8,589,662'Accepting or rolling back execution of instructions based on comparing predicted and actual dependency control signals'2013 8,151,092'Control signal memoization in a multiple instruction issue microprocessor'2012 8,141,020'Temperature-controlled 3-dimensional bus placement'2012 8,108,714'Method and system for soft error recovery during processor execution'2012 8,091,050'Modeling system-level effects of soft errors'2012 7,958,334'Method and apparatus for an efficient multi-path trace cache design'2011 7,930,525'Method and apparatus for an efficient multi-path trace cache design'2011 7,921,331'Write filter cache method and apparatus for protecting the microprocessor core from soft errors'2011 7,865,699'Method and apparatus to extend the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code'2011 7,774,654'Method and apparatus for preventing soft error accumulation in register arrays'2010 7,552,277'Distributed buffer integrated cache memory organization and method for reducing energy consumption thereof'2009 7,506,216'System and method of workload-dependent reliability projection and monitoring for microprocessor chips and systems'2009 7,496,733'System and method of execution of register pointer instructions ahead of instruction issues'2009 7,493,523'Method and apparatus for preventing soft error accumulation in register arrays'2009 7,472,038'Method of predicting microprocessor lifetime reliability using architecture-level structure-aware techniques'2008 7,461,209'Transient cache storage with discard function for disposable data'2008 7,454,573'Cost-conscious pre-emptive cache line displacement and relocation mechanisms'2008 7,454,316'Method and apparatus for monitoring and enhancing on-chip microprocessor reliability'2008 7,444,544'Write filter cache method and apparatus for protecting the microprocessor core from soft errors'2008 7,366,875'Method and apparatus for an efficient multi-path trace cache design'2008 7,340,588'Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code'2008 7,325,124'System and method of execution of register pointer instructions ahead of instruction issue'2008 7,130,963'System and method for instruction memory storage and processing based on backwards branch control information'2006 7,076,681'Processor with demand-driven clock throttling power reduction'2006 6,948,051'Method and apparatus for reducing logic activity in a microprocessor using reduced bit width slices that are enabled or disabled depending on operation width'2005 6,711,651'Method and apparatus for history-based movement of shared-data in coherent cache memories of a multiprocessor system using push prefetching'2004 6,678,795'Method and apparatus for memory prefetching based on intra-page usage history'2004

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2004–2019Patents assigned to IBM (41)· patent assignee history

2004Based in Peekskill, NY, US· patent location history

2005Based in Cortland, NY, US· patent location history

2006–2019Based in Cortlandt Manor, NY, US· patent location history

2012–2019Patents assigned to RIVERS JUDE A (12)· patent assignee history

2012–2016Patents assigned to KURSUN EREN (6)· patent assignee history

2012–2019Patents assigned to BOSE PRADIP (5)· patent assignee history

2012–2016Patents assigned to EMMA PHILIP G (5)· patent assignee history

2012–2013Based in Yorktown Heights, NY, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	41	2004–2019
RIVERS JUDE Aself	12	2012–2019
KURSUN EREN	6	2012–2016
BOSE PRADIP	5	2012–2019
EMMA PHILIP G	5	2012–2016

Locations

Location	Patents	Span
Cortlandt Manor, New York, US	38	2006–2019
Yorktown Heights, New York, US	2	2012–2013
Peekskill, New York, US	2	2004
Cortland, New York, US	1	2005