LexDanaLexDanabeta
Inventor

Kerim Kalafala

Inventor
Rhinebeck, NY, US

Overview

80→
Patents
2006–2021
Patent span
Physics
Primary field (CPC G)

Patents· 80 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing89%
H04LTransmission of digital information, e.g. telegraphic communication9%
G01RMeasuring electric variables2%
PatentTitleYear
11,017,137Efficient projection based adjustment evaluation in static timing analysis of integrated circuits202110,970,447Leverage cycle stealing within optimization flows202110,929,567Parallel access to running electronic design automation (EDA) application202110,902,167Feedback-aware slack stealing across transparent latches empowering performance optimization of digital integrated circuits202110,891,412Offline analysis of hierarchical electronic design automation derived data202110,747,925Variable accuracy incremental timing analysis202010,606,970Selection of corners and/or margins using statistical static timing analysis of an integrated circuit202010,552,562Leverage cycle stealing within optimization flows202010,540,465Leverage cycle stealing within optimization flows202010,387,682Parallel access to running electronic design automation (EDA) application201910,380,289Multi-sided variations for creating integrated circuits201910,380,286Multi-sided variations for creating integrated circuits201910,372,851Independently projecting a canonical clock201910,354,046Programmable clock division methodology with in-context frequency checking201910,346,569Multi-sided variations for creating integrated circuits201910,325,059Incremental common path pessimism analysis201910,318,683Clock domain-independent abstracts201910,289,776Sensitivity calculation filtering for statistical static timing analysis of an integrated circuit201910,216,875Leverage cycle stealing within optimization flows201910,169,526Incremental parasitic extraction for coupled timing and power optimization201910,169,503Callback based constraint processing for clock domain independence201910,031,985Sensitivity calculation filtering for statistical static timing analysis of an integrated circuit201810,013,516Selection of corners and/or margins using statistical static timing analysis of an integrated circuit20189,985,843Efficient parallel processing of a network with conflict constraints between nodes20189,977,850Callback based constraint processing for clock domain independence20189,959,382Adaptive characterization and instantiation of timing abstracts20189,922,149'Integration of functional analysis and common path pessimism removal in static timing analysis'20189,916,405'Distributed timing analysis of a partitioned integrated circuit design'20189,910,954'Programmable clock division methodology with in-context frequency checking'20189,864,824'System and method for efficient statistical timing analysis of cycle time independent tests'20189,858,383'Incremental parasitic extraction for coupled timing and power optimization'20189,853,866Efficient parallel processing of a network with conflict constraints between nodes20179,852,246System and method for efficient statistical timing analysis of cycle time independent tests20179,836,572Incremental common path pessimism analysis20179,798,850'System and method for combined path tracing in static timing analysis'20179,785,737'Parallel multi-threaded common path pessimism removal in multiple paths'20179,767,239'Timing optimization driven by statistical sensitivites'20179,754,062'Timing adjustments across transparent latches to facilitate power reduction'20179,710,594'Variation-aware timing analysis using waveform construction'20179,646,122'Variable accuracy parameter modeling in statistical timing'20179,639,654'Managing virtual boundaries to enable lock-free concurrent region optimization of an integrated circuit'20179,607,124'Method of hierarchical timing closure employing dynamic load-sensitive feedback constraints'20179,608,868'Efficient parallel processing of a network with conflict constraints between nodes'20179,600,617'Automated timing analysis'20179,594,868'Scaling voltages in relation to die location'20179,569,571'Method and system for timing violations in a circuit'20179,542,524'Static timing analysis (STA) using derived boundary timing constraints for out-of-context (OOC) hierarchical entity analysis and abstraction'20179,519,747'Dynamic and adaptive timing sensitivity during static timing analysis using look-up table'20169,501,609'Selection of corners and/or margins using statistical static timing analysis of an integrated circuit'20169,495,218'Efficient parallel processing of a network with conflict constraints between nodes'20169,495,497'Dynamic voltage frequency scaling'20169,483,604'Variable accuracy parameter modeling in statistical timing'20169,430,603'Scaling voltages in relation to die location'20169,418,201'Integration of functional analysis and common path pessimism removal in static timing analysis'20169,400,864'System and method for maintaining slack continuity in incremental statistical timing analysis'20169,342,639'Method of hierarchical timing closure of VLSI circuits using partially disruptive feedback assertions'20169,280,624'System and method for efficient statistical timing analysis of cycle time independent tests'20168,775,988'Decentralized dynamically scheduled parallel static timing analysis'20148,776,004'Method for improving static timing analysis and optimizing circuits using reverse merge'20148,689,158'System and method for performing static timing analysis in the presence of correlations between asserted arrival times'20148,578,310'Method of measuring the impact of clock skew on slack during a statistical static timing analysis'20138,381,150'Method for performing a parallel static timing analysis using thread-specific sub-graphs'20138,141,014'System and method for common history pessimism relief during static timing analysis'20128,122,404'Performing a statistical timing abstraction for a hierarchical timing analysis of VLSI circuits'20128,112,735'Affinity-based clustering of vectors for partitioning the columns of a matrix'20128,108,816'Device history based delay variation adjustment during static timing analysis'20128,056,038'Method for efficiently checkpointing and restarting static timing analysis of an integrated circuit chip'20117,987,440'Method and system for efficient validation of clock skews during hierarchical static timing analysis'20117,958,484'Affinity-based clustering of vectors for partitioning the columns of a matrix'20117,844,933'Methods of optimizing timing of signals in an integrated circuit design using proxy slack values'20107,797,657'Parameter ordering for multi-corner static timing analysis'20107,784,003'Estimation of process variation impact of slack in multi-corner path-based static timing analysis'20107,698,674'System and method for efficient analysis of point-to-point delay constraints in static timing'20107,694,254'Method, computer program product, and apparatus for static timing with run-time reduction'20107,681,157'Variable threshold system and method for multi-corner static timing analysis'20107,669,156'Method of identifying paths with delays dominated by a particular factor'20107,555,740'Method and system for evaluating statistical sensitivity credit in path-based hybrid multi-corner static timing analysis'20097,353,359'Affinity-based clustering of vectors for partitioning the columns of a matrix'20087,353,477'Method of identifying paths with delays dominated by a particular factor'20087,117,466'System and method for correlated process pessimism removal for static timing analysis'2006

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2006–2021Patents assigned to IBM (79)· patent assignee history
2006–2021Based in Rhinebeck, NY, US· patent location history
2012–2014Patents assigned to KALAFALA KERIM (9)· patent assignee history
2012–2014Patents assigned to HATHAWAY DAVID J (6)· patent assignee history
2012–2014Patents assigned to VISWESWARIAH CHANDRAMOULI (5)· patent assignee history
2012–2014Patents assigned to HEMMETT JEFFREY G (3)· patent assignee history
2012–2018Based in Rhineback, NY, US· patent location history
2012Based in Hopewell Junction, NY, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM792006–2021
KALAFALA KERIMself92012–2014
HATHAWAY DAVID J62012–2014
VISWESWARIAH CHANDRAMOULI52012–2014
HEMMETT JEFFREY G32012–2014
Locations
LocationPatentsSpan
Rhinebeck, New York, US762006–2021
Rhineback, New York, US22012–2018
Hopewell Junction, New York, US22012