Inventor
Atul C. Ajmera
Inventor
Wappingers Falls, NY, US
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices43%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1034%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests9%
C23CCoating metallic material2%
PatentTitleYear
8,461,009'Spacer and process to enhance the strain in the channel with stress liner'20137,759,206'Methods of forming semiconductor devices using embedded L-shape spacers'20107,741,165'Polycrystalline SiGe Junctions for advanced devices'20107,387,924'Polycrystalline SiGe junctions for advanced devices'20087,135,391'Polycrystalline SiGe junctions for advanced devices'20067,091,128'Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs'20066,991,979'Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs'20066,900,092'Surface engineering to prevent epi growth on gate poly during selective epi processing'20056,642,156'Method for forming heavy nitrogen-doped ultra thin oxynitride gate dielectrics'20036,605,521'Method of forming an oxide film on a gate side wall of a gate structure'20036,602,759'Shallow trench isolation for thin silicon/silicon-on-insulator substrates by utilizing polysilicon'20036,566,198'CMOS structure with non-epitaxial raised source/drain and self-aligned gate and method of manufacture'20036,566,210'Method of improving gate activation by employing atomic oxygen enhanced oxidation'20036,521,947'Method of integrating substrate contact on SOI wafers with STI process'20036,506,649'Method for forming notch gate having self-aligned raised source/drain structure'20036,503,833'Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed thereby'20036,440,807'Surface engineering to prevent EPI growth on gate poly during selective EPI processing'20026,437,377'Low dielectric constant sidewall spacer using notch gate process'20026,255,145'Process for manufacturing patterned silicon-on-insulator layers with self-aligned trenches and resulting product'20016,057,220'Titanium polycide stabilization with a porous barrier'20006,013,583'Low temperature BPSG deposition process'20005,747,866'Application of thin crystalline Si.sub.3 N.sub.4 liners in shallow trench isolation (STI) structures'19985,643,823'Application of thin crystalline Si.sub.3 N.sub.4 liners in shallow trench isolation (STI) structures'1997Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1997–2013Patents assigned to IBM (23)· patent assignee history
1997–1998Patents assigned to SIEMENS AG (2)· patent assignee history
1997–2006Based in Wappinger Falls, NY, US· patent location history
2000–2013Based in Wappingers Falls, NY, US· patent location history
2010–2013Patents assigned to CHARTERED SEMICONDUCTOR MFG (2)· patent assignee history
2013Patents assigned to AJMERA ATUL C (1)· patent assignee history
2013Patents assigned to BAIOCCO CHRISTOPHER V (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 23 | 1997–2013 |
| CHARTERED SEMICONDUCTOR MFG | 2 | 2010–2013 |
| SIEMENS AG | 2 | 1997–1998 |
| AJMERA ATUL Cself | 1 | 2013 |
| BAIOCCO CHRISTOPHER V | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Wappingers Falls, New York, US | 18 | 2000–2013 |
| Wappinger Falls, New York, US | 5 | 1997–2006 |